12-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC) - ADC12J4000

ADC12J4000 (ACTIVE)

12-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC)

 

Description

The ADC12J4000 device is a wideband sampling and digital tuning device. Texas Instruments’ giga-sample analog-to-digital converter (ADC) technology enables a large block of frequency spectrum to be sampled directly at RF. An integrated DDC (Digital Down Converter) provides digital filtering and down-conversion. The selected frequency block is made available on a JESD204B serial interface. Data is output as baseband 15-bit complex information for ease of downstream processing. Based on the digital down-converter (DDC) decimation and link output rate settings, this data is output on 1 to 5 lanes of the serial interface.

A DDC bypass mode allows the full rate 12-bit raw ADC data to also be output. This mode of operation requires 8 lanes of serial output.

The ADC12J4000 device is available in a 68-pin VQFN package. The device operates over the Industrial (–40°C ≤ TA ≤ 85°C) ambient temperature range.

Features

  • Excellent Noise and Linearity up to and beyond FIN = 3 GHz
  • Configurable DDC
  • Decimation Factors from 4 to 32 (Complex Baseband Out)
  • Usable Output Bandwidth of 800 MHz at
    4x Decimation and 4000 MSPS
  • Usable Output Bandwidth of 100 MHz at
    32x Decimation and 4000 MSPS
  • Bypass Mode for Full Nyquist Output Bandwidth
  • Low Pin-Count JESD204B Subclass 1 Interface
  • Automatically Optimized Output Lane Count
  • Embedded Low Latency Signal Range Indication
  • Low Power Consumption
  • Key Specifications:
    • Max Sampling Rate: 4000 MSPS
    • Min Sampling Rate: 1000 MSPS
    • DDC Output Word Size: 15-Bit Complex (30 bits total)
    • Bypass Output Word Size: 12-Bit Offset Binary
    • Noise Floor: −149 dBFS/Hz or −150.8 dBm/Hz
    • IMD3: −64 dBc (FIN = 2140 MHz ± 30 MHz at −13 dBFS)
    • FPBW (–3 dB): 3.2 GHz
    • Peak NPR: 46 dB
    • Supply Voltages: 1.9 V and 1.2 V
    • Power Consumption
      • Bypass (4000 MSPS): 2 W
      • Decimate by 10 (4000 MSPS): 2 W
      • Power Down Mode: <50 mW

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Parametrics Compare all products in High Speed ADCs (>10MSPS)

 
Resolution (Bits)
Sample Rate (Max) (MSPS)
# Input Channels
SNR (dB)
ENOB (Bits)
SFDR (dB)
Power Consumption (Typ) (mW)
Input Range (Vp-p)
Interface
Operating Temperature Range (C)
Analog Input BW (MHz)
Input Buffer
Package Group
Package Size: mm2:W x L (PKG)
Rating
SINAD (dB)
Architecture
DNL (Typ) (+/-LSB)
INL (Typ) (+/-LSB)
Reference Mode
ADC12J4000 ADC12J1600 ADC12J2700
12    12    12   
4000    1600    2700   
1    1    1   
55    55    55   
8.8    8.8    8.8   
71    70    71   
2000    1600    1800   
0.725    0.725    0.725   
JESD204B    JESD204B    JESD204B   
-40 to 85    -40 to 85    -40 to 85   
3300    3300    3300   
Yes    Yes    Yes   
VQFN    VQFN    VQFN   
68VQFN: 100 mm2: 10 x 10(VQFN)    68VQFN: 100 mm2: 10 x 10(VQFN)    68VQFN: 100 mm2: 10 x 10(VQFN)   
Catalog    Catalog    Catalog   
54.8    54.8    54.8   
Folding Interpolating    Folding Interpolating    Folding Interpolating   
0.25    0.25    0.25   
2    2    2   
Int    Int    Int