SLUSDQ4 April 2019 BQ79606A-Q1
The Cell Balancing input are connected to internal balance FET through balancing resistor. The resistor sets the balance current. Connect CBn to VCn if not used. The CB pins must NEVER be connected to cell voltages (module connectors) that are expected to be less than the recommended operating condition. The internal FET diode will conduct and likely damage the FET in reverse voltage conditions. CB0 can not be left floating at any condition.
If a connection to cell1 negative terminal is open the IC bias current will flow through the CB1/VC1 pins and then to the cell2 negative module terminal, causing CB1 and VC1 pins to go below the minimum voltage recommended with respect to pin AVSS. This violates device spec. If the module connector ground pin can float while the other module terminals are still connected it is recommended that a schottky diode be added between CB1 and device GND (AVSS) to ensure that CB1 and VC1 pin voltage does not violate the absolute maximum limits.