SLUSDQ4 April 2019 BQ79606A-Q1
PRODUCTION DATA.
COMM_UART_TR_STAT1 Register Address: 0x271 | |||||||
B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
SENTH[7] | SENTH[6] | SENTH[5] | SENTH[4] | SENTH[3] | SENTH[2] | SENTH[1] | SENTH[0] |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R | R | R | R | R | R | R | R |
SENTH[7:0] | High byte of the counter for response frames transmitted over the UART interface. Counter saturates when COMM_UART_TR_STAT1[SENTH] and COMM_UART_TR_STAT2[SENTL] reach 0xFFFF. This counter is reset and the register is cleared when read. All of the COMM_UART_*_* registers are updated and latched when COMM_UART_RC_STAT3 is read to ensure all counter data refers to the same period of time. |