SLUSDQ4 April 2019 BQ79606A-Q1
The SPI master has a loopback function that is enabled using the DIAG_CTRL1[SPI_LOOPBACK] bit. When enabled, the byte in the SPI_TX register is clocked directly to the MISO pin of the SPI master to verify the SPI master functionality. This is done internally, so no external connection is required to run this test. This verifies that the SPI function is working correctly. The SPI_CFG, SPI_TX, and SPI_EXE registers are written as a normal SPI transaction, but the external pins do not toggle during this mode. The expected result of the test is that the byte in the SPI_TX register is read into the SPI_RX register. The SS pin is latched to the setting in SPI_CFG[SS_STAT] that existed when the LOOPBACK mode was enabled. The CPHA and CPOL parameters must be set before entering LOOPBACK mode to ensure proper operation. Changing the CPOL or CPHA parameters while in LOOPBACK mode may result in errant pulses on the SPI outputs and is not recommended.