SLUSDQ4 April 2019 BQ79606A-Q1
PRODUCTION DATA.
COMM_UART_RR_FLT_MSK Register Address: 0x0A | |||||||
B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
SPARE[1] | SPARE[0] | SPARE | SPARE | SOF_MSK | BERR_MSK | SPARE | CRC_MSK |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
RW | RW | RW | RW | RW | RW | RW | RW |
SPARE[1:0] | Spare | ||||||
SPARE | Spare | ||||||
SPARE | Spare | ||||||
SOF_MSK | Enables mask for COMM_UART_RR_FAULT[SOF]
0: Mask disabled 1: Mask enabled to prevent fault signaling |
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BERR_MSK | Enables mask for COMM_UART_RR_FAULT[BERR]
0: Mask disabled 1: Mask enabled to prevent fault signaling |
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SPARE | Spare | ||||||
CRC_MSK | Enables mask for COMM_UART_RR_FAULT[CRC]
0: Mask disabled 1: Mask enabled to prevent fault signaling |