SLUSDQ4 April 2019 BQ79606A-Q1
The master is programmed using a combination of writes. A first write must be done to the SPI_CFG register to configure the master for the transaction. The SPI_CFG[SPI_EN] bit is used to enable the SPI master interface, the SPI_CFG[SS_STAT] bit is used to select the slave device, and finally, the SPI_CFG[NUMBITS] sets how many bits the transaction is (1-bit to 8-bit transaction). SPI_CFG[NUMBITS] is only read by the device when the SPI_GO command is executed. After the SPI is configured, write to the SPI_EXE[SPI_GO] bit to execute the transaction. Once the SPI_EXE[SPI_GO] is written to a '1', a SPI transaction of a length set by SPI_CFG[NUMBITS] is executed. The SPI_CFG[SS_STAT] write and the SPI_EXE[SPI_GO] write must be two separate transaction to guarantee a properly executed transaction. The transaction writes the bits in the SPI_TX register to the slave device and simultaneously reads the bits from the slave device to the SPI_RX register. For an 8-bit write, the full byte is used. For less than 8-bit transactions, the write is done starting with the LSB and the read updates starting with LSB. For example, for a 3-bit transaction, bits 2:0 of the register SPI_TX are written to MOSI while the bits 2:0 of SPI_RX updated with the read data from MISO. Due to the simultaneous read and write of the data, the SPI master supports both types of SPI devices. For devices where read/write are separate transactions, SPI_RX is a "don't care" when a write is done. Multiple writes or read are possible while the SS pin of a particular device is selected. This enables support for SPI slaves that larger than 8-bit transactions. Multiple transactions must be done while SS is selected to complete larger than 8-bit transactions. Once the read or write is complete, set the SPI_CFG[SS_STAT] bit to end the transaction.
It should be noted that before the SPI_CFG[SPI_EN] bit is set, the SPI interface pins are configured by the GPIO*_CONF registers. This could lead to invalid states on the SPI pins (from the SPI interface perspective). For example, if the GPIO*_CONF registers have GPIO3 configured as an input, with the SPI function disabled GPIO3 (SS) may be low, selecting the slave device without intending to. If this is an issue for the application, use an external pull up to VIO to ensure the correct state for the slave. Once SPI is enabled, all of the GPIOs are set in accordance to the SPI_CFG register.
Do not change the CPHA (SPI_CFG[CPHA]/CPOL (SPI_CFG[CPOL]) values and the SS output (SPI_CFG[SS_STAT]) in a single write transaction as this may result in changing the idle clock value while SS is active which results in a faulty communication.