SLUSDQ4 April 2019 BQ79606A-Q1
During on-demand reads, the host enables the desired cells using the CELL_ADC_CTRL register. After this register is updated, the host must wait at least tDLY(COM) before sending a second write to set the CONTROL2[CELL_ADC_GO] bit to start the cell conversion. When the CELL_ADC_GO bit is set, the CELL ADCs simultaneously start the conversion with the enabled cell channels. The cell voltage conversions happen simultaneously. The results are available as the individual conversions complete. The DEV_STAT[CELL_STAT] bit is set while the respective ADCs are running. Once all of the cell conversions are complete, the CELL_STAT bit is cleared and after the result(s) are updated in the registers the DEV_STAT[DRDY_CELL] bit is set. The host is ensured that the register information is current and may read the results from the conversion (read the H byte register to update the M and L bytes). If the host reads from the register prior to the conversion finishing, the 0x8000 diagnostic result is read. Writing to the CONTROL2[CELL_ADC_GO] bit during a cell conversion terminates the current conversion and begins a new conversion.