SLUSDQ4 April 2019 BQ79606A-Q1
There are several memory locations that are programmable in non-volatile memory (NVM) using OTP. The OTP is loaded in both the factory and customer space with every reset event to supply the defaults for the corresponding register space. A reset occurs whenever a WAKE tone or WAKEUP is received by the device. Additionally, the host may perform a reset to the OTP defaults by writing the CONTROL1[SOFT_RESET] bit. Writing this bit resets all of the registers to the OTP programmed value. Error check and correction (ECC, both single error correction, SEC and double error detection, DED) is performed during both the factory and customer space OTP load. Any load errors of the customer OTP space signal a fault using the OTP_FAULT[CUSTLDERR]. Similarly, any load errors of the factory OTP space signal a fault using the OTP_FAULT[FACTLDERR]. Additionally, the OTP space (factory and customer) are protected from data integrity problems using CRC. If any over-voltage error conditions exist in the OTP pages space (factory and customer) , the OTP_FAULT[GBLOVERR] bit is set. Information received from the device with this error must not be considered reliable.