SLUSDQ4 April 2019 BQ79606A-Q1
In addition to the SINC3 filter, a digital implementation of a simple, first-order, single pole (RC) filter is also included. The implementation is shown in Figure 7. This filter allows for much lower corner frequencies for the digital filter and the implementation does not require a fixed point multiplication stage. This filter always uses the corrected VREF value coming from the SINC3 filter. When enabled, the cell ADCs are run in continuous mode with the minimum interval setting, updating the uncorrected non filtered (VCELL*_HU, VCELL*_MU, and VCELL*_LU), the corrected non filtered (VCELL*H and VCELL*L), and the corrected and filtered (VCELL*_LF and VCELL*_HF) registers every time the host reads High byte (H).
The corner frequency of the single pole digital filter is set with the CELL_ADC_CONF1[FILSHIFT] bits, as shown in Table 2.
|CELL_ADC_CONF1[FILSHIFT]||Typical Corner Frequency (Hz) DR=256||Typical Corner Frequency (Hz) DR=128||Typical Corner Frequency (Hz) DR=64||Typical Corner Frequency (Hz) DR=32|
The single pole digital filter responds in the same way as an analog RC circuit responds, meaning that unless conversions are run continuously through the filter there is a step response that must be taken into account before reading the value for the first time. The step response of each corner frequency setting is shown below. This step response should be taken into account whenever starting up the conversions after coming out of SLEEP or SHUTDOWN modes or a significant jump in the input. Once the output voltage gets through the step response the host can read the voltage at any time interval to have a snapshot of the cell voltage.