SLUSDQ4 April 2019 BQ79606A-Q1
PRODUCTION DATA.
COMM_COML_FAULT Register Address: 0x29E | |||||||
B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
RSVD[1] | RSVD[0] | BERR | DATA_MISS | DATA_ORDER | SYNC2 | SYNC1 | BIT |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R | R | R | R | R | R | R | R |
RSVD[1:0] | Reserved | ||||||
BERR | Indicates that the byte error has occurred in a received byte on the COMH interface. BERR is set when a COMH received byte has the byte error bit set, or when a received byte has detected one or more error during demodulation such as sync1, sync2, bit, data_order or data_miss error.This is also can be set when a received data is interrupted by a transmit transit byte (came from UART to VIF, valid only on the base device).
0: No fault 1: Fault |
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DATA_MISS | Indicates that there has been a failure to detect a ‘1’ or ‘0’ on the COML bus when one was expected. DATA_MISS is set if a valid data value is not received for longer that the expected bit time.
0: No fault 1: Fault |
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DATA_ORDER | Indicates that at least one of the received data bits on the COML bus does not have the expected complement bit structure. See the "Daisy Chain" section for more details.
0: No fault 1: Fault |
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SYNC2 | Indicates that the timing information extracted from the demodulation of the preamble half-bit and the two full bits of synchronization on the COML bus is outside of the expected window. It is likely that the data is not sampled correctly. This error indicates noise has corrupted the timing infomration in the first bits of the communicated data.
0: No fault 1: Fault |
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SYNC1 | Indicates that the demodulation of the preamble half-bit and the two full bits of synchronization data on the COML bus have errors and the timing is likely not correct. This error indicates noise has corrupted the timing infomration in the first bits of the communicated data. Clear this fault bit any time the vertical interface is disabled and then re-enabled.
0: No fault 1: Fault |
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BIT | Indicates that the demodulation of the COML bus traffic has received a data bit which is not a strong '1' or '0'. Occurs when not enough samples are received to gauarantee a solid logic level, or if a bit is corrupted due to noise.
0: No fault 1: Fault |