SLUSDQ4 April 2019 BQ79606A-Q1
PRODUCTION DATA.
COMM_COMH_RC_STAT2 Register Address: 0x276 | |||||||
B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
VALIDL[7] | VALIDL[6] | VALIDL[5] | VALIDL[4] | VALIDL[3] | VALIDL[2] | VALIDL[1] | VALIDL[0] |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R | R | R | R | R | R | R | R |
VALIDL[7:0] | High byte of the valid command counter for received command frames from the COMH interface. Valid commands are command frames with no errors and a vaild CRC. Counter saturates when COMM_COMH_RC_STAT1[VALIDH] and COMM_COMH_RC_STAT2[VALIDL] reach 0xFFFF. The counter is reset and register is cleared when read. All of the COMM_COMH_*_STAT* registers are updated and latched when COMM_COMH_RC_STAT1 is read to ensure all counter data refers to the same period of time. |