SLUSDQ4 April 2019 BQ79606A-Q1
PRODUCTION DATA.
AUX_ADC_CONF Register Address: 0x26 | |||||||
B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
SPARE[3] | SPARE[2] | SPARE[1] | SPARE[0] | DR[1] | DR[0] | ADC_FREQ[1] | ADC_FREQ[0] |
0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 |
RW | RW | RW | RW | RW | RW | RW | RW |
SPARE[3:0] | Spare | ||||||
DR[1:0] | Sets decimation ratio for ADC
00: 32 01: 64 10: 128 11: 256 |
||||||
ADC_FREQ[1:0] | Selects ADC sample frequency (applies to all ADCs)
00: 1 MHz 01: Reserved (1MHz operation) 10: Reserved (1MHz operation) 11: Reserved (1MHz operation) |