SLUSDQ4 April 2019 BQ79606A-Q1
The BQ79606A-Q1 GPIOs are configurable as a SPI master interface. The master is used to control devices such as an external OTP or the Active Balancing Chipset (EMB1428/EMB1499) from Texas Instruments. The SPI interface includes four I/Os: clock (SCLK), master data output (MOSI), master data input (MISO), and the slave select (SS). Three of the lines are shared by all devices on the SPI bus: SCLK, MOSI and MISO. SCLK is generated by the BQ79606A-Q1 (fSCLK) and is used for synchronization. MOSI and MISO are the data lines.
Each stack device is configurable to be a SPI master. The result looks something like Figure 34.
The SPI timing diagram is shown in Figure 35.
Clock polarity (CPOL) and clock phase (CPHA) define the SPI bus clock format. These are programmable for the BQ79606A-Q1 using the SPI_CFG[CPOL] and SPI_CFG[CPHA] bits. The SPI clock is inverted/non-inverted depending on CPOL parameter. The CPHA parameter shifts the sampling phase. While SPI_CFG[CPHA]=0, MISO and MOSI are sampled on the leading (first) clock edge. When SPI_CFG[CPHA]=1, MISO and MOSI are sampled on the trailing (second) clock edge, regardless of whether that clock edge is rising or falling. The following sections outline the behavior of CPHA and CPOL.