SLUSDQ4 April 2019 BQ79606A-Q1
A window comparator is integrated to monitor the GPIO1 to GPIO6 inputs for over-temperature and under-temperature conditions in the cells. When enabled, the comparator cycles through each of the temperature sense inputs and compares the voltage to thresholds programmed in the OTUT_THRESH register. This comparator function is entirely separated from the ADC function and as such, even if the ADC function fails, the analog comparators flag the crossing of the (register selectable) under-temperature and over-temperature comparator thresholds. The thresholds and deglitch timing are programmable and apply for all six inputs. Two internal DACs set the separate over-temperature and under-temperature thresholds. The OT threshold is programmable to OFF or from 20% to 35% of TSREF in steps of 1% using the OTUT_THRESH[OT_THRESH] bits. The UT threshold is programmable to OFF or from 60% to 75% of TSREF in steps of 1% using the OTUT_THRESH[UT_THRESH] bits. TSREF must be enabled (CONTROL2[TSREF_EN]=1) for at least 2ms (for the recommended capacitor value, larger capacitors may lead to longer startup time) before enabling the OT/UT function. Failure to do so results in all of the OT_FAULT and UT_FAULT bits being set. Additionally, if a TSREF OV/UV fault happens at any time during OT/UT operation, all of the OT_FAULT and UT_FAULT bits are set.
Use the OTUT_CTRL register to enable the GPIOs that are required for OT/UT monitoring. Use the CONTROL2[OTUT_EN] bit to enable the comparators. When enabled, all of the configuration bits are read. Further changes to the registers have no effect until the OTUT_EN bit is cleared and set again.
Once enabled, the comparators are monitored in a "round-robin" fashion, starting with GPIO1 and cycling through to GPIO6. The total time taken to do the round-robin cycle is tCYCLE. The monitoring time for each GPIO input is tRR_SLOT. The LOOP_STAT[OTUT_LOOP_DONE] bit is updated at the end of each round-robin cycle (including the BIST, if enabled. See CB_DONE, OVUV, and OTUT Built-In Self Test (BIST) for details). If already set, the bit remains as 1 until cleared by a read.
The deglitch time for the OT and UT comparators is programmed using the COMP_DG[TEMP_DG] bits. The deglitch is a count up/down style deglitch. During the monitoring cycle, the comparator checks the voltage. A counter is incremented when the comparator is tripped, and decremented when the comparator is not tripped. Once the counter reaches the programmed threshold, the OT_FAULT[GPIO*] or UT_FAULT[GPIO*] bit (depending on which comparator trips) is updated, and, if unmasked, the NFAULT output (for base device) and/or the FAULT* interface (for the stack device) signals the fault. Note that due to the round-robin architecture, the total delay for an OT or UT event may be as high as: (tCYCLE-tRR_SLOT)+ 0.1ms.