General
Review and verify the following for the custom
schematic design:
- Reviewed above "Common checklist for all sections" section of the
user's guide.
- Number of attached devices supported.
- Connection of address, clock, control and data signals.
- Connection and routing topology followed based on number of memory devices
connected.
- Connection of signals based on the selected memory size.
- Differential clock termination.
- DDR reference voltage resistor divider.
- Value of the VTT resistors and filter capacitors used.
- VTT Termination for address and control signals when x2 memory devices are
used.
- Connection of DDRSS RESETn signal to DDR_RESETn memory reset input.
- Connection of ODT signal from DDRSS to memory device (external pull is
optional).
- Connection of Alert, TEN, ZQn and DDR0_CAL0 pins.
- Swapping of Data bits and data groups.
Schematic Review
Follow the below list for the custom schematic
design:
- x1 16-bit and x2 8-bit are the supported memory configuration.
- The recommendation is to compare the bulk and decoupling capacitors used and
values with SK schematic implementation.
- Supply railss connected to the processor DDRSS peripheral supply rail and
the attached memory device IO follow the processor and attached memory
device ROC.
- Connection of address, clock, control and data signals, as per the AM62x,
AM62Lx DDR Board Design and Layout Guidelines.
- Routing topology followed based on number of memory devices connected ((data
bus topology is always point-to-point), (x1 16-bit, point-to-point and x2
8-bit, daisy for address and control)).
- Connection of signals based on the selected memory size (CS0, CS1, BG0, BG1,
refer AM62x, AM62Lx DDR Board Design and Layout Guidelines).
- Differential clock termination using x2 resistors and filter capacitor.
- Value of the VTT resistors and filter capacitors used.
- DDR reference voltage resistor divider value and tolerance. Resistor divider
connection (1kΩ, ±1%) for DDR reference DDR_VREFCA generation. The
recommendation is to place a decoupling capacitor 0.1μF across the resistors
and near to the memory pin.
- VTT Termination for address and control signals when x2 memory devices are
used (optional for x1 memory device) and VTT termination supply (LDO)
implementation. VTT LDO implementation. VTT resistors and capacitors (1
capacitor for every 2 VTT resistors) quantity and value (The recommendation
is to follow TMDS64EVM).
- Connection of DDRSS RESETn signal to DDR_RESETn memory reset input (to hold
the signal low during power-on initialization). The recommendation is to add
a pulldown (10kΩ) for DDRSS RESETn signal and placed near the memory device
reset input pin.
- Connection of Alert (10kΩ pullup) and TEN (1kΩ pulldown) signals.
- ZQ0, ZQ1, Memory device IO calibration resistor (240Ω, ±1%) connection
across ZQ and VSS.
- DDR0_CAL0, DDRSS IO pad calibration resistor (240Ω, ±1%) connected across
DDR0_CAL0 and VSS.
- Connection of ODT signal from DDRSS to memory device (external pull is
optional).
- Follow AM62x, AM62Lx DDR Board Design and Layout Guidelines when data
bits and data groups are swapped.
Additional
- The recommendation is to refer TMDS64EVM for
implementing VTT terminations for DDR4 address and control signals and VTT
supply (LDO).
- The recommendation is to add layout notes on the
schematic (the recommendation is to follow the AM62x, AM62Lx DDR Board Design
and Layout Guidelines).
- The recommendation is to follow the Pin
Connectivity Requirements section of the processor-specific data sheet
for connecting unused DDRSS interface signals.
- Connection of required DDRSS signals to the
memory device for expansion.