JAJSKP5A December 2020 – September 2021 TAS2764
PRODUCTION DATA
The gain from audio input to speaker terminals is controlled by setting the amplifier’s output level and digital volume control (DVC).
Amplifier output level settings are programmed using AMP_LEVEL[4:0] register bits. The levels are presented in the Register Map in dBV (dB relative to 1 Vrms), with a full scale digital audio input (0 dBFS) and the DVC set by default to 0 dB. It should be noted that these levels may not be achievable because of analog clipping in the amplifier, so they should be used to convey gain only.
Equation 1 below calculates amplifier output voltage:
VAMP= INPUT+ADVC+AAMP
where
The digital volume control (DVC) is configurable from 0 dB to -100 dB in 0.5 dB steps by setting the DVC_LVL[7:0] register bits. Settings greater than C8h are interpreted as mute. When a change in digital volume control occurs, the device ramps the volume to the new setting based on the DVC_RAMP_RATE[1:0] register bits status. If DVC_RAMP_RATE[1:0] bits are set to 2'b11 the volume ramping is disabled. This setting can be used to speed up startup, shutdown and digital volume changes when volume ramping is handled by the system master.
The Class-D amplifier uses a closed-loop architecture, so the gain does not depend on power supply. The approximate threshold for the onset of analog clipping is calculated in Equation 2.
where
When VBAT1S supplies class-D output stage typical RFET value is 1 Ω. For PVDD supply RFET typical value is 0.5 Ω.