JAJSKP5A December   2020  – September 2021 TAS2764

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 TDM Port Timing Requirements
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Feature Description
      1. 8.3.1 Device Address Selection
      2. 8.3.2 General I2C Operation
      3. 8.3.3 Register Organization
    4. 8.4  Device Functional Modes
      1. 8.4.1  TDM Port
      2. 8.4.2  Playback Signal Path
        1. 8.4.2.1  High Pass Filter
        2. 8.4.2.2  Amplifier Inversion
        3. 8.4.2.3  Digital Volume Control and Amplifier Output Level
          1. 8.4.2.3.1 Safe Mode
        4. 8.4.2.4  VBAT1S Supply
        5. 8.4.2.5  Low Voltage Signaling (LVS)
        6. 8.4.2.6  Y-Bridge
        7. 8.4.2.7  Noise Gate
        8. 8.4.2.8  Supply Tracking Limiter with Brown Out Prevention
          1. 8.4.2.8.1 Supply Tracking Limiter
          2. 8.4.2.8.2 Brownout Prevention (BOP)
        9. 8.4.2.9  Inter Chip Gain Alignment
          1. 8.4.2.9.1 Inter-Chip Communication (ICC) Pin
        10. 8.4.2.10 Class-D Settings
          1. 8.4.2.10.1 Synchronization and EMI
      3. 8.4.3  SAR ADC
      4. 8.4.4  Current and Voltage (IV) Sense
      5. 8.4.5  Post Filter Feed-Back (PFFB)
      6. 8.4.6  Load Diagnostics
      7. 8.4.7  Thermal Foldback
      8. 8.4.8  Over Power Protection
      9. 8.4.9  Clocks and PLL
      10. 8.4.10 Echo Reference
    5. 8.5  Operational Modes
      1. 8.5.1 Hardware Shutdown
      2. 8.5.2 Mode Control and Software Reset
      3. 8.5.3 Software Shutdown
      4. 8.5.4 Mute
      5. 8.5.5 Active
      6. 8.5.6 Diagnostic
      7. 8.5.7 Noise Gate
    6. 8.6  Faults and Status
      1. 8.6.1 Faults and Status over TDM
    7. 8.7  Power Sequencing Requirements
    8. 8.8  Digital Input Pull Downs
    9. 8.9  Register Map
      1. 8.9.1   Register Summary Table Page=0x00
      2. 8.9.2   Register Summary Table Page=0x01
      3. 8.9.3   Register Summary Table Page=0x04
      4. 8.9.4   PAGE (page=0x00 address=0x00) [reset=00h]
      5. 8.9.5   SW_RESET (page=0x00 address=0x01) [reset=00h]
      6. 8.9.6   MODE_CTRL (page=0x00 address=0x02) [reset=1Ah]
      7. 8.9.7   CHNL_0 (page=0x00 address=0x03) [reset=28h]
      8. 8.9.8   DC_BLK0 (page=0x00 address=0x04) [reset=21h]
      9. 8.9.9   DC_BLK1 (page=0x00 address=0x05) [reset=41h]
      10. 8.9.10  MISC_CFG1 (page=0x00 address=0x06) [reset=00h]
      11. 8.9.11  MISC_CFG2 (page=0x00 address=0x07) [reset=20h]
      12. 8.9.12  TDM_CFG0 (page=0x00 address=0x08) [reset=09h]
      13. 8.9.13  TDM_CFG1 (page=0x00 address=0x09) [reset=02h]
      14. 8.9.14  TDM_CFG2 (page=0x00 address=0x0A) [reset=0Ah]
      15. 8.9.15  LIM_MAX_ATTN (page=0x00 address=0x0B) [reset=80h]
      16. 8.9.16  TDM_CFG3 (page=0x00 address=0x0C) [reset=10h]
      17. 8.9.17  TDM_CFG4 (page=0x00 address=0x0D) [reset=13h]
      18. 8.9.18  TDM_CFG5 (page=0x00 address=0x0E) [reset=42h]
      19. 8.9.19  TDM_CFG6 (page=0x00 address=0x0F) [reset=40h]
      20. 8.9.20  TDM_CFG7 (page=0x00 address=0x10) [reset=04h]
      21. 8.9.21  TDM_CFG8 (page=0x00 address=0x11) [reset=05h]
      22. 8.9.22  TDM_CFG9 (page=0x00 address=0x12) [reset=06h]
      23. 8.9.23  TDM_CFG10 (page=0x00 address=0x13) [reset=08h]
      24. 8.9.24  TDM_CFG11 (page=0x00 address=0x14) [reset=0Ah]
      25. 8.9.25  ICC_CNFG2 (page=0x00 address=0x15) [reset=00h]
      26. 8.9.26  TDM_CFG12 (page=0x00 address=0x16) [reset=12h]
      27. 8.9.27  ICLA_CFG0 (page=0x00 address=0x17) [reset=0Ch]
      28. 8.9.28  ICLA_CFG1 (page=0x00 address=0x18) [reset=00h]
      29. 8.9.29  DG_0 (page=0x00 address=0x19) [reset=0Dh]
      30. 8.9.30  DVC (page=0x00 address=0x1A) [reset=00h]
      31. 8.9.31  LIM_CFG0 (page=0x00 address=0x1B) [reset=22h]
      32. 8.9.32  LIM_CFG1 (page=0x00 address=0x1C) [reset=32h]
      33. 8.9.33  BOP_CFG0 (page=0x00 address=0x1D) [reset=40h]
      34. 8.9.34  BOP_CFG1 (page=0x00 address=0x1E) [reset=32h]
      35. 8.9.35  BOP_CFG2 (page=0x00 address=0x1F) [reset=02h]
      36. 8.9.36  BOP_CFG3 (page=0x00 address=0x20) [reset=06h]
      37. 8.9.37  BOP_CFG4 (page=0x00 address=0x21) [reset=2Ch]
      38. 8.9.38  BOP_CFG5 (page=0x00 address=0x22) [reset=4Ch]
      39. 8.9.39  BOP_CFG6 (page=0x00 address=0x23) [reset=20h]
      40. 8.9.40  BOP_CFG7 (page=0x00 address=0x24) [reset=02h]
      41. 8.9.41  BOP_CFG8 (page=0x00 address=0x25) [reset=06h]
      42. 8.9.42  BOP_CFG9 (page=0x00 address=0x26) [reset=32h]
      43. 8.9.43  BOP_CFG10 (page=0x00 address=0x27) [reset=46h]
      44. 8.9.44  BOP_CFG11 (page=0x00 address=0x28) [reset=20h]
      45. 8.9.45  BOP_CFG12 (page=0x00 address=0x29) [reset=02h]
      46. 8.9.46  BOP_CFG13 (page=0x00 address=0x2A) [reset=06h]
      47. 8.9.47  BOP_CFG14 (page=0x00 address=0x2B) [reset=38h]
      48. 8.9.48  BOP_CFG15 (page=0x00 address=0x2C) [reset=40h]
      49. 8.9.49  BOP_CFG17 (page=0x00 address=0x2D) [reset=20h]
      50. 8.9.50  BOP_CFG18 (page=0x00 address=0x2E) [reset=02h]
      51. 8.9.51  BOP_CFG19 (page=0x00 address=0x2F) [reset=06h]
      52. 8.9.52  BOP_CFG20 (page=0x00 address=0x30) [reset=3Eh]
      53. 8.9.53  BOP_CFG21 (page=0x00 address=0x31) [reset=37h]
      54. 8.9.54  BOP_CFG22 (page=0x00 address=0x32) [reset=20h]
      55. 8.9.55  BOP_CFG23 (page=0x00 address=0x33) [reset=FFh]
      56. 8.9.56  BOP_CFG24 (page=0x00 address=0x34) [reset=E6h]
      57. 8.9.57  NG_CFG0 (page=0x00 address=0x35) [reset=BDh]
      58. 8.9.58  NG_CFG1 (page=0x00 address=0x36) [reset=ADh]
      59. 8.9.59  LVS_CFG0 (page=0x00 address=0x37) [reset=A8h]
      60. 8.9.60  DIN_PD (page=0x00 address=0x38) [reset=03h]
      61. 8.9.61  IO_DRV0 (page=0x00 address=0x39) [reset=FFh]
      62. 8.9.62  IO_DRV1 (page=0x00 address=0x3A) [reset=FFh]
      63. 8.9.63  INT_MASK0 (page=0x00 address=0x3B) [reset=FCh]
      64. 8.9.64  INT_MASK1 (page=0x00 address=0x3C) [reset=BEh]
      65. 8.9.65  INT_MASK4 (page=0x00 address=0x3D) [reset=DFh]
      66. 8.9.66  INT_MASK2 (page=0x00 address=0x40) [reset=F6h]
      67. 8.9.67  INT_MASK3 (page=0x00 address=0x41) [reset=00h]
      68. 8.9.68  INT_LIVE0 (page=0x00 address=0x42) [reset=00h]
      69. 8.9.69  INT_LIVE1 (page=0x00 address=0x43) [reset=00h]
      70. 8.9.70  INT_LIVE1_0 (page=0x00 address=0x44) [reset=00h]
      71. 8.9.71  INT_LIVE2 (page=0x00 address=0x47) [reset=00h]
      72. 8.9.72  INT_LIVE3 (page=0x00 address=0x48) [reset=00h]
      73. 8.9.73  INT_LTCH0 (page=0x00 address=0x49) [reset=00h]
      74. 8.9.74  INT_LTCH1 (page=0x00 address=0x4A) [reset=00h]
      75. 8.9.75  INT_LTCH1_0 (page=0x00 address=0x4B) [reset=00h]
      76. 8.9.76  INT_LTCH2 (page=0x00 address=0x4F) [reset=00h]
      77. 8.9.77  INT_LTCH3 (page=0x00 address=0x50) [reset=00h]
      78. 8.9.78  INT_LTCH4 (page=0x00 address=0x51) [reset=00h]
      79. 8.9.79  VBAT_MSB (page=0x00 address=0x52) [reset=00h]
      80. 8.9.80  VBAT_LSB (page=0x00 address=0x53) [reset=00h]
      81. 8.9.81  PVDD_MSB (page=0x00 address=0x54) [reset=00h]
      82. 8.9.82  PVDD_LSB (page=0x00 address=0x55) [reset=00h]
      83. 8.9.83  TEMP (page=0x00 address=0x56) [reset=00h]
      84. 8.9.84  INT_CLK_CFG (page=0x00 address=0x5C) [reset=19h]
      85. 8.9.85  MISC_CFG3 (page=0x00 address=0x5D) [reset=80h]
      86. 8.9.86  CLOCK_CFG (page=0x00 address=0x60) [reset=0Dh]
      87. 8.9.87  IDLE_IND (page=0x00 address=0x63) [reset=48]
      88. 8.9.88  MISC_CFG4 (page=0x00 address=0x65) [reset=08]
      89. 8.9.89  TG_CFG0 (page=0x00 address=0x67) [reset=00h]
      90. 8.9.90  CLK_CFG (page=0x00 address=0x68) [reset=7Fh]
      91. 8.9.91  LV_EN_CFG (page=0x00 address=0x6A) [reset=12h]
      92. 8.9.92  NG_CFG2 (page=0x00 address=0x6B) [reset=01h]
      93. 8.9.93  NG_CFG3 (page=0x00 address=0x6C) [reset=00h]
      94. 8.9.94  NG_CFG4 (page=0x00 address=0x6D) [reset=00h]
      95. 8.9.95  NG_CFG5 (page=0x00 address=0x6E) [reset=1Ah]
      96. 8.9.96  NG_CFG6 (page=0x00 address=0x6F) [reset=00h]
      97. 8.9.97  NG_CFG7 (page=0x00 address=0x70) [reset=96h]
      98. 8.9.98  PVDD_UVLO (page=0x00 address=0x71) [reset=00h]
      99. 8.9.99  DAC_MOD_RST (page=0x00 address=0x76) [reset=02h]
      100. 8.9.100 REV_ID (page=0x00 address=0x7D) [reset=30h]
      101. 8.9.101 I2C_CKSUM (page=0x00 address=0x7E) [reset=00h]
      102. 8.9.102 BOOK (page=0x00 address=0x7F) [reset=00h]
      103. 8.9.103 LSR (page=0x01 address=0x19) [reset=40h]
      104. 8.9.104 SDOUT_HIZ_1 (page=0x01 address=0x3D) [reset=00h]
      105. 8.9.105 SDOUT_HIZ_2 (page=0x01 address=0x3E) [reset=00h]
      106. 8.9.106 SDOUT_HIZ_3 (page=0x01 address=0x3F) [reset=00h]
      107. 8.9.107 SDOUT_HIZ_4 (page=0x01 address=0x40) [reset=00h]
      108. 8.9.108 SDOUT_HIZ_5 (page=0x01 address=0x41) [reset=00h]
      109. 8.9.109 SDOUT_HIZ_6 (page=0x01 address=0x42) [reset=00h]
      110. 8.9.110 SDOUT_HIZ_7 (page=0x01 address=0x43) [reset=00h]
      111. 8.9.111 SDOUT_HIZ_8 (page=0x01 address=0x44) [reset=00h]
      112. 8.9.112 SDOUT_HIZ_9 (page=0x01 address=0x45) [reset=00h]
      113. 8.9.113 TG_EN (page=0x01 address=0x47) [reset=ABh]
      114. 8.9.114 DG_DC_VAL1 (page=0x04 address=0x08) [reset=40h]
      115. 8.9.115 DG_DC_VAL2 (page=0x04 address=0x09) [reset=26h]
      116. 8.9.116 DG_DC_VAL3 (page=0x04 address=0x0A) [reset=40h]
      117. 8.9.117 DC_DG_VAL4 (page=0x04 address=0x0B) [reset=00h]
      118. 8.9.118 LIM_TH_MAX1 (page=0x04 address=0x0C) [reset=68h]
      119. 8.9.119 LIM_TH_MAX2 (page=0x04 address=0x0D) [reset=00h]
      120. 8.9.120 LIM_TH_MAX3 (page=0x04 address=0x0E) [reset=00h]
      121. 8.9.121 LIM_TH_MAX4 (page=0x04 address=0x0F) [reset=00h]
      122. 8.9.122 LIM_TH_MIN1 (page=0x04 address=0x10) [reset=28h]
      123. 8.9.123 LIM_TH_MIN2 (page=0x04 address=0x11) [reset=00h]
      124. 8.9.124 LIM_TH_MIN3 (page=0x04 address=0x12) [reset=00h]
      125. 8.9.125 LIM_TH_MIN4 (page=0x04 address=0x13) [reset=00h]
      126. 8.9.126 LIM_INF_PT1 (page=0x04 address=0x14) [reset=56h]
      127. 8.9.127 LIM_INF_PT2 (page=0x04 address=0x15) [reset=66h]
      128. 8.9.128 LIM_INF_PT3 (page=0x04 address=0x16) [reset=66h]
      129. 8.9.129 LIM_INF_PT4 (page=0x04 address=0x17) [reset=00h]
      130. 8.9.130 LIM_SLOPE1 (page=0x04 address=0x18) [reset=10h]
      131. 8.9.131 LIM_SLOPE2 (page=0x04 address=0x19) [reset=00h]
      132. 8.9.132 LIM_SLOPE3 (page=0x04 address=0x1A) [reset=00h]
      133. 8.9.133 LIM_SLOPE4 (page=0x04 address=0x1B) [reset=00h]
      134. 8.9.134 TF_HLD1 (page=0x04 address=0x1C) [reset=00h]
      135. 8.9.135 TF_HLD2 (page=0x04 address=0x1D) [reset=03h]
      136. 8.9.136 TF_HLD3 (page=0x04 address=0x1E) [reset=E8h]
      137. 8.9.137 TF_HLD4 (page=0x04 address=0x1F) [reset=00h]
      138. 8.9.138 TF_RLS1 (page=0x04 address=0x20) [reset=40h]
      139. 8.9.139 TF_RLS2 (page=0x04 address=0x21) [reset=12h]
      140. 8.9.140 TF_RLS3 (page=0x04 address=0x22) [reset=E0h]
      141. 8.9.141 TF_RLS4 (page=0x04 address=0x23) [reset=00h]
      142. 8.9.142 TF_SLOPE1 (page=0x04 address=0x24) [reset=04h]
      143. 8.9.143 TF_SLOPE2 (page=0x04 address=0x25) [reset=08h]
      144. 8.9.144 TF_SLOPE3 (page=0x04 address=0x26) [reset=89h]
      145. 8.9.145 TF_SLOPE4 (page=0x04 address=0x27) [reset=00h]
      146. 8.9.146 TF_TEMP_TH1 (page=0x04 address=0x28) [reset=39h]
      147. 8.9.147 TF_TEMP_TH2 (page=0x04 address=0x29) [reset=80h]
      148. 8.9.148 TF_TEMP_TH3 (page=0x04 address=0x2A) [reset=00h]
      149. 8.9.149 TF_TEMP_TH4 (page=0x04 address=0x2B) [reset=00h]
      150. 8.9.150 TF_MAX_ATTN1 (page=0x04 address=0x2C) [reset=2Dh]
      151. 8.9.151 TF_MAX_ATTN2 (page=0x04 address=0x2D) [reset=6Ah]
      152. 8.9.152 TF_MAX_ATTN3 (page=0x04 address=0x2E) [reset=86h]
      153. 8.9.153 TF_MAX_ATTN4 (page=0x04 address=0x2F) [reset=00h]
      154. 8.9.154 LD_CFG0 (page=0x04 address=0x40) [reset=02h]
      155. 8.9.155 LD_CFG1 (page=0x04 address=0x41) [reset=ADh]
      156. 8.9.156 LD_CFG2 (page=0x04 address=0x42) [reset=B7h]
      157. 8.9.157 LD_CFG3 (page=0x04 address=0x43) [reset=00h]
      158. 8.9.158 LD_CFG4 (page=0x04 address=0x44) [reset=00h]
      159. 8.9.159 LD_CFG5 (page=0x04 address=0x45) [reset=1Bh]
      160. 8.9.160 LD_CFG6 (page=0x04 address=0x46) [reset=6Eh]
      161. 8.9.161 LD_CFG7 (page=0x04 address=0x47) [reset=00h]
      162. 8.9.162 CLD_EFF_1 (page=0x04 address=0x48) [reset=6Ch]
      163. 8.9.163 CLD_EFF_2 (page=0x04 address=0x49) [reset=CCh]
      164. 8.9.164 CLD_EFF_3 (page=0x04 address=0x4A) [reset=CDh]
      165. 8.9.165 CLD_EFF_4 (page=0x04 address=0x4B) [reset=00h]
      166. 8.9.166 LDG_RES1 (page=0x04 address=0x4C) [reset=00h]
      167. 8.9.167 LDG_RES2 (page=0x04 address=0x4D) [reset=00h]
      168. 8.9.168 LDG_RES3 (page=0x04 address=0x4E) [reset=00h]
      169. 8.9.169 LDG_RES4 (page=0x04 address=0x4F) [reset=00h]
    10. 8.10 SDOUT Equations
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
    3. 9.3 Design Requirements
    4. 9.4 Detailed Design Procedure
      1. 9.4.1 Mono/Stereo Configuration
      2. 9.4.2 EMI Passive Devices
    5. 9.5 Application Curves
  10. 10Initialization Set Up
    1. 10.1 Recommended Configuration at Power Up
    2. 10.2 Initial Device Configuration - 4 Channel Power Up (Default Mode - PWR_MODE1)
    3. 10.3 Initial Device Configuration - 44.1 kHz
    4. 10.4 Sample Rate Change - 48 kHz to 44.1kHz
    5. 10.5 Idle Channel Hysterisis
    6. 10.6 DSP Loopback
  11. 11Power Supply and I2C Recommendations
    1. 11.1 Power Supply Modes
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 サポート・リソース
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Faults and Status

During the power-up sequence, the circuit monitoring the AVDD pin (UVLO) will hold the device in reset (including all configuration registers) until the supply is valid. The device will not exit hardware shutdown until AVDD is valid and the SDZ pin is released. Once SDZ is released, the digital core voltage regulator will power up, enabling detection of the operational mode. If AVDD dips below the UVLO threshold, the device will immediately be forced into a reset state.

The device also monitors the PVDD supply and holds the analog core in power down if the supply is below the UVLO threshold (set by register bits PVDD_UVLO_TH[5:0]). If the TAS2764 is in active operation and an UVLO fault occurs, the analog blocks will immediately be powered down to protect the device. These faults are latched and require a transition through HW/SW shutdown to clear the fault. The latched registers will report UVLO faults.

The device transitions into software shutdown mode if it detects any faults with the TDM clocks such as:

• Invalid SBCLK to FSYNC ratio

• Invalid FSYNC frequency

• Halting of SBCLK or FSYNC clocks

Upon detection of a TDM clock error, the device transitions into software shutdown mode as quickly as possible to limit the possibility of audio artifacts. Once all TDM clock errors are resolved, the device volume ramps back to its previous playback state. During a TDM clock error, the IRQZ pin will assert low if the clock error interrupt mask register bit IM_TDMCE is set low. The clock fault is also available for read-back in the latched fault status registers (bits IL_TDMCE and IR_TDMCE]). Reading the latched fault status register clears the register.

The TAS2764 also monitors die temperature and Class-D load current and will enter software shutdown mode if either of these exceed safe values. As with the TDM clock error, the IRQZ pin will assert low for these faults if the appropriate fault interrupt mask register bit is set low for over temperature and for over current. The fault status can also be monitored in the latched fault registers as with the TDM clock error.

Over temperature warnings and flags are not raised if the device is in Idle or Noise Gate mode.

The status registers (and IRQZ pin if enabled via the status mask register) also indicate limiter behavior including when the limiter is activated, when PVDD is below the inflection point, when maximum attenuation has been applied, when the limiter is in infinite hold and when the limiter has muted the audio.

In the situations when the device operates in PWR_MODE2 or PWR_MODE4, the VBAT1S pin is supplied by an internal LDO. Protection circuits monitor this block and generate faults in case of under voltage, over voltage or if the LDO is over loaded. There is no re-try if one of these faults triggers; the device goes into shut down and the IRQZ pin will go low.

The IRQZ pin is an open drain output that asserts low during unmasked fault conditions and therefore must be pulled up with a resistor to IOVDD. An internal pull up resistor is provided in the TAS2764 and can be accessed by setting the IRQZ_PU register bit high. Figure 8-12 below highlights the IRQZ pin circuit.

GUID-B1DF8E4C-7099-4781-AC1F-A5A11EA80B55-low.gifFigure 8-12 IRQZ Pin

The IRQZ interrupt configuration can be set using IRQZ_PIN_CFG[1:0] register bits. The IRQZ_POL register bit sets the interrupt polarity and IRQZ_CLR register bit allows to clear the interrupt latch register bits.

Live flag registers are active only when the device is in active mode of operation. If the device is put in shutdown by I2C command or due to any fault condition described below, the live flags will be reset. Latched flags will not be reset in this condition and available for user to read their status.

Table 8-5 Fault Interrupt Mask
Interrupt Live Register Latch Register Mask Register Default (1 = Mask)
Temp Over 105C IL_TO105 IR_TO105 IM_TO105 1
Temp Over 115C IL_TO115 IR_TO115 IM_TO115 1
Temp Over 125C IL_TO125 IR_TO125 IM_TO125 1
Temp Over 135C IL_TO135 IR_TO135 IM_TO135 1
Over Temp Error Device in shutdown IR_OT IM_OT 0
Over Current Error Device in shutdown IR_OC IM_OC 0
TDM Clock Error IL_TDMCE IR_TDMCE IM_TDMCE 1
TDM Clock Error: Invalid SBCLK ratio or FS rate IR_TDMCEIR
TDM Clock Error: FS changed on the fly IR_TDNCEFC
TDM Clock Error: SBCLK FS ratio changed on the fly IR_TDMCERC
BOP Active IL_BOPA IR_BOPA IM_BOPA 0
BOP Level 0 Active IL_BOPL0A IR_BOPL0A IM_BOPL0A 0
BOP Level 1 Active IL_BOPL1A IR_BOPL1A IM_BOPL1A 0
BOP Level 2 Active IL_BOPL2A IR_BOPL2A IM_BOPL2A 0
BOP Level 3 Active IL_BOPL3A IR_BOPL3A IM_BOPL3A 0
BOP Infinite Hold IL_BOPIH IR_BOPIH IM_BOPIH 0
BOP Mute IL_BOPM IR_BOPM IM_BOPM 0
PVDD Below LImiter Inflection IL_PBIP IR_PBIP IM_PBIP 0
Limiter Active IL_LIMA IR_LIMA IM_LIMA 0
Limiter Max Atten IL_LIMMA IR_LIMMA IM_LIMMA 0
PVDD UVLO Device in shutdown IR_PUVLO IM_PUVLO 0
VBAT1S UVLO Device in shutdown IR_VBAT1S_UVLO IM_VBAT1S_UVLO 0
OTP CRC Error Device in shutdown IR_OTPCRC
Load Diagnostic Complete IM_LDC 1
Load Diagnostic Open/Short Load IM_SOL[1:0] [11]
Brownout Device Power Down IM_BOPD 1
Internal PLL Clock Error Device in shutdown IR_PLL_CLK IM_PLL_CLK 1
Noise Gate Active IL_NGA
PVDD-VBAT1S Below Threshold IL_PVBT IR_PVBT IM_PVBT 0
Internal VBAT1S LDO Over Voltage Device in shutdown IR_LDO_OV IM_LDO_OV 1
Internal VBAT1S LDO Under Voltage Device in shutdown IR_LDO_UV IM_LDO_UV 0
Internal VBAT1S LDO Over Load Device in shutdown IR_LDO_OL IM_LDO_OL 1
Thermal Detector Threshold 2 IL_TDTH2 IR_TDTH2 IM_TDTH2 0
Thermal Detector Threshold 1 IL_TDTH1 IR_TDTH1 IM_TDTH1 0