JAJSKP5A December 2020 – September 2021 TAS2764
PRODUCTION DATA
During power up and power down PVDD voltage must be greater than (VBAT1S-0.7V)
Once all supplies are stable the SDZ pin can be set high to initialize the part. After a hardware or software reset additional commands to the device should be delayed for at least 1 mS to allow the OTP memory to load.
If the TDM clocks are sent to TAS2764 after the part is programmed through I2C to go to Active Mode the TDM clock interrupts will be triggered.
When VBAT1S is internally generated (see below Section 11.1) it is recommended that the device enters Software Shutdown mode before entering Hardware Shutdown mode. This ensures that VBAT1S pin is discharged using the internal 5 kOhms pull down resistor (not present in HW shutdown mode).