SLUUD63A December 2024 – October 2026 BQ41Z90
| Class | Subclass | Name | Type | Min | Max | Default | Unit |
|---|---|---|---|---|---|---|---|
| Settings | Fuse | PF Fuse D | H1 | 0x00 | 0xFF | 0x00 | Hex |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSVD | RSVD | RSVD | RSVD | RSVD | RSVD | RSVD | RSVD |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD | VSS | VREF | TS | TMPC | DFW | PFFORCE | RSVD |
| Fuse blow action for PFStatus() bits: | ||
| RSVD (Bit 7): Reserved. Don't use. | ||
| VSS (Bit 6): Vss failure | ||
| 1 = | Enabled | |
| 0 = | Disabled (default) | |
| VREF (Bit 5): Vref failure | ||
| 1 = | Enabled | |
| 0 = | Disabled (default) | |
| TS (Bit 4): Themistor failure | ||
| 1 = | Enabled | |
| 0 = | Disabled (default) | |
| TMPC (Bit 3): TMP468 communication failure | ||
| 1 = | Enabled | |
| 0 = | Disabled (default) | |
| DFW (Bit 2): DF wearout | ||
| 1 = | Enabled | |
| 0 = | Disabled (default) | |
| PFFORCE (Bit 1): Manual PF | ||
| 1 = | Enabled | |
| 0 = | Disabled (default) | |
| RSVD (Bit 0): Reserved. Don't use. | ||