| ASCDL (Bit 7): Short Circuit in Discharge—PF Enable |
|
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
| AOCCL (Bit 6): Over Circuit in
Charge—PF Enable |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
| AOCDL (Bit 5): Over Current in
Discharge—PF Enable |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
| VIMA (Bit 4): Voltage Imbalance Active |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
| VIMR (Bit 3): Voltage Imbalance At Rest |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
| CD (Bit 2): Capacity Degradation |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
| IMP (Bit 1): Cell impedance |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
| CB (Bit 0): Cell balancing |
| 1 = | Enabled |
| 0 = | Disabled (default) |