| RSVD (Bits 31–30): Reserved. Do not use. |
|
| OCDL (Bit 29): Overcurrent in discharge
latch |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| COVL (Bit 28): Cell overvoltage latch |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| UTD (Bit 27): Undertemperature during discharge |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| UTC (Bit 26): Undertemperature during charge |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| PCHGC (Bit 25): Over-precharge current |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| CHGV (Bit 24): Overcharging voltage |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| CHGC (Bit 23): Overcharging current |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| OC (Bit 22): Overcharge |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| RSVD (Bit 21): Reserved. Do not use. |
|
| CTO (Bit 20): Charge timeout |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| RSVD (Bit 19): Reserved. Do not use. |
| | |
| PTO (Bit 18): Precharge timeout |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| HWDF (Bit 17): SBS Host watchdog timeout |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| OTF (Bit 16): Overtemperature FET |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| RSVD (Bit 15): Reserved. Do not
use. |
| | |
| CUVC (Bit 14): Cell undervoltage compensated |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| OTD (Bit 13): Overtemperature during discharge |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| OTC (Bit 12): Overtemperature during charge |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| ASCDL (Bit 11): AFE Short-circuit
during discharge latch |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| ASCD (Bit 10): AFE Short-circuit during
discharge |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| AOCCL (Bit 9): AFE Over current during
charge latch |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| AOCC (Bit 8): AFE Over current during
charge |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| AOCDL (Bit 7): AFE Over current during
discharge latch |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| AOCD (Bit 6): AFE Over current during
discharge |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| OCD2 (Bit 5): Overcurrent during discharge 2 |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| OCD1 (Bit 4): Overcurrent during discharge 1 |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| OCC2 (Bit 3): Overcurrent during charge 2 |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| OCC1 (Bit 2): Overcurrent during charge 1 |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| COV (Bit 1): Cell overvoltage |
| 1 = | Detected |
| 0 = | Not detected |
| | |
| CUV (Bit 0): Cell undervoltage |
| 1 = | Detected |
| 0 = | Not detected |