Trace length in Ethernet PHY design refers to the physical length of the copper tracks on a PCB connecting the Ethernet PHY (physical layer) chip to the magnetic modules (transformers) and the RJ45 jack, or to the MAC (media access control) chip. The RGMII specification operates at a clock frequency of 125MHz. Since RGMII utilizes double data rate (DDR) signaling, data is sampled on both the rising and falling edges of the clock. This DDR signaling creates a narrow 4.0ns data window.

To attain clean data latching and maximum setup and hold margins, the clock signal must arrive exactly in the center of this data window (a center-aligned clock, requiring a 1.5ns to 2.0ns delay relative to the data).

Depending on the hardware architecture, this timing alignment can be achieved using one of two methods:

1. RGMII v1.3 (physical trace delay): The transmitting device outputs clock and data signals edge-aligned (arriving at the same time). To achieve the required 1.5–2.0ns center alignment, the hardware engineer must manually add the physical trace length to the clock line on the PCB. This method is deprecated and not recommended for modern layouts.
2. RGMII v2.0 / RGMII-ID (internal delay): The internal delay feature compensates for RGMII trace length mismatches on the PCB. RGMII uses source-synchronous clocking where the clock and data must arrive at the receiver within a tight timing window (typically ±0.5ns). When the PCB traces clock and data have different lengths, this difference introduces skew that can violate the setup and hold margins of the receiver. CPSW_CONTROL.RGMII*_ID_MODE, when set to 1, enables the internal delay mode for the transmit path of the corresponding RGMII port. This mode provides a phase shift of a quarter cycle between clock and data.

For AM26x devices, internal delay can be enabled using SYSCFG.

Writing 1'b1 disables the internal clock delays, and those delays must be handled onboard.

A similar internal delay feature is also available from a PHY perspective. There are timing path operating modes. Timing paths can operate in either aligned mode or shift mode. Aligned mode introduces zero clock skew. Shift mode allows clock skew adjustments in ≅0.25ns increments through the register settings. Configure these modes using the RGMII control register (RGMIICTL) at 0x0032. If using shift mode, adjust the specific clock skew values using the RGMII delay control register (RGMIIDCTL) at address 0x0086. This entirely depends on the PHY being used. Please refer to the PHY datasheet for more details.

The ENET-LLD PHY drivers provide support for these extended configurations. Extended configurations are PHY specific configurations. For example, the dp83867 PHY supports such features. This can be utilized by configuring the extended configuration data structure.

typedef struct Dp83867_Cfg_s
 {
 /*! Enable TX clock shift */
 bool txClkShiftEn;
 /*! Enable RX clock shift */
 bool rxClkShiftEn;
 /*! TX delay value */
 uint32_t txDelayInPs;
 /*! RX delay value */
 uint32_t rxDelayInPs;
 /*! ...other fields */
 } Dp83867_Cfg;

There is provision for configuring extended configurations in SYSCFG for AM26x devices.

Users can also check the Timing Requirements section in the PHY datasheet and verify that the board design adheres to the same timing requirements.