The CPSW subsystem provides Ethernet communication with hardware switching capabilities compliant to the IEEE 802.3 (Ethernet Working Group) standard. CPSW3G on AM26x devices supports 10Mbps, 100Mbps, or 1000Mbps operations with a selectable MII, RMII, or RGMII.

Port Architecture

• Port-0 (host port): Port-0 is a CPDMA and CPPI between the CPU and MAC ports. All packets to and from the Arm Cortex-R5F core traverse this port.
• Port-1 and Port-2 (external MAC ports): Port-1 and Port-2 are physical Ethernet interfaces that support MII, GMII, RMII, RGMII, SGMII, and QSGMII.

SYSCFG automatically generates code and ENET-LLD handles the initial configuration. The application layer performs additional runtime configuration as necessary. Any packet entering the device externally enters through either the MAC port-1 or MAC port-2. If the packet is meant to be consumed by the device, the packet is forwarded to the host port. If the packet is meant to be sent to another port, the packet is switched to the other MAC port.

CPSW Sub-blocks

The CPSW subsystem is comprised of these smaller blocks:

• CPDMA: The packet DMA controller handles transfers between the host port and the Arm Cortex-R5F core. The CPDMA implements Ethernet ports that support a line-rate bandwidth interface compliant to TI's CPPI 3.0 and CBA 3.1 transfer standards.
• ALE (address look-up engine): The ALE processes incoming packets using a port number, destination and source MAC, EtherType, and VLAN information. The ALE has an output port-mask that indicates the forwarding destinations. The ALE is critical for packet routing and filtering.
• Interrupt controller: The interrupt controller handles six interrupt sources, including TX/RX packet events, per-port statistical updates, link status changes, ECC errors, and ALE events.
• Statistic module: This module includes hardware counters that track per-port statistics. The module captures good and bad frame counts, drop counts (ALE overrun, FIFO overrun, fragmentation, portmask drops, oversized or undersized frames), and CRC and alignment errors.
• CPTS (common platform timesync): The CPTS is the timestamping engine for TX/RX packets. Timing events are pushed to the CPSW FIFO circuit for gPTP and TSN operations.
• MDIO (management data input/output): The serial management interface that controls the external PHY devices according to IEEE 802.3 (Standard for Ethernet). The MDIO handles the PHY configuration (link speed, duplex, power), status monitoring (link up or down), and automatic negotiation.

Packet Classification

CPSW hardware can classify packets based on the following:

• Destination MAC address
• Source MAC address
• VLAN ID and priority
• EtherType
• Destination and source IP header fields
• A combination of the parameters in this list

Based on the above list, a variety of rules can be set for consuming, forwarding, or dropping a packet on MAC ports. The CPSW also supports hardware-based modification of some of the above fields of the frame—offloading this operation from the CPU or software.

VLAN Support

Hardware VLAN tagging and filtering enables logical network segmentation. CPSW supports the following:

• Insertion and removal of the VLAN tags
• Packet classification based on the VLAN
• Inter-VLAN and Intra-VLAN routing in hardware
• Broadcast domain isolation

Use-cases include isolating the control plane from the traffic of the data plane, prioritizing safety-critical messages, and multi-tenant communication over shared physical infrastructure.

Rate Limiting

Policers enforce bandwidth limits at the ingress and egress of each MAC port. Packets that exceed the configured thresholds are dropped or remarked. Policers are essential for preventing congestion and maintaining fairness and deterministic latency in time-sensitive applications. Policers combined with QoS and VLAN tagging, provides complete traffic management for industrial Ethernet systems.