Bootstrap (strapping) pins configure the PHY behavior during power-up, before any MDIO communication occurs. These pins are sampled once at power-on or reset, with the logic levels determined by external resistors. Getting bootstrap configuration incorrect is a common cause of Ethernet failures that are difficult to diagnose.

Common Bootstrap Settings:

• PHY Address: Sets the MDIO address (typically 0-31). The address must match the address that the software expects. Verify the software configures the PHY address that is bootstrapped in the hardware.
  • Figure 4-1 PHY Address Configuration
• Interface Mode: Selects RGMII, RMII, MII, and so forth. The interface mode must match the MAC configuration.
  • Figure 4-2 Pin MUX Configuration

Common Issues:

• Wrong resistor values: Using 4.7k instead of 10k can result in marginal logic levels that fail intermittently or at temperature extremes.
• Floating pins: Missing pull-up resistors cause undefined behavior. Some Ethernet PHYs have weak internal pullups, and these pull-up resistors are unreliable.
• Incorrect pullup direction: A pullup occurs where a pulldown is required and puts the PHY in the wrong mode entirely.

Verification Steps:

1. Check the bootstrap table of the PHY in the appropriate datasheet. Compare the required resistor values and configurations against the appropriate schematic.
2. Measure bootstrap pin voltages during power-up with an oscilloscope or multimeter. Verify the voltages reach valid logic high (>2.0V) or low (<0.8V) levels.
3. Read the PHY configuration registers through the MDIO after initialization. Compare the actual mode (interface type, address) against the expected values.
4. If the bootstrap settings are incorrect, check for schematic errors, incorrect resistor population, or PCB shorts or opens.

Bootstrap Versus MDIO Conflicts:

Some PHY configuration parameters can only be set using bootstrap and are locked after power-up. Interface mode selection (RGMII, RMII, MII) is typically bootstrap-only. If software attempts to configure these parameters differently through MDIO, the PHY silently ignores the writes, creating a mismatch between software expectations and actual hardware state.

Debug Approach:

• Read back the PHY registers after MDIO configuration to verify writes took effect.
• Compare bootstrap-configured interface mode against software configuration.
• Check if MDIO writes to read-only registers are returning unexpected values.
• Verify PHY datasheet specifies which settings are bootstrap-only versus MDIO-configurable.

Auto-negotiation Bootstrap:

Many PHYs provide bootstrap pins to enable or disable auto-negotiation or force specific speeds (10Mbps, 100Mbps, or 1000Mbps). Incorrect bootstrap configuration can disable auto-negotiation when software expects that auto-negotiation is enabled, or force a speed incompatible with the link partner. This manifests as a link never establishing or establishing at the wrong speed.

Debug Approach:

• Read the PHY basic control register (register 0x00) to verify the current auto-negotiation state.
• Check if the auto-negotiation complete bit is set in the basic status register (0x01).
• Verify bootstrap matches the auto-negotiation configuration of the software.
• Test with forced speed or duplex on both link partners to isolate auto-negotiation issues.
• The CPSW3G variant supports two external MAC ports, each requiring a PHY with a unique MDIO address. Each PHY must be bootstrapped to a different address (typically 0 and 1, or 0 and 3). Common failures occur when both PHYs share the same bootstrap address, causing MDIO bus collisions where both PHYs respond simultaneously, corrupting read data.
• Read the PHY ID registers (0x02, 0x03) at each expected address and verify the correct PHY responds (refer to section xx.xx to learn how to read PHY registers).
• Check if an unexpected PHY responds at the wrong address (indicates incorrect bootstrap).
• Use the MDIO bus analyzer or scope to detect multiple PHYs driving the bus simultaneously.
• Verify bootstrap resistors are independent for each PHY, not shared on same net.
• Confirm the software MDIO address configuration matches the PHY bootstrap addresses.