SLUUDO2 September   2026 AM2611 , AM2612 , AM2612-Q1 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Acronyms
  5. 2Introduction
  6. 3Introduction to CPSWSS and ENET-LLD
    1. 3.1 Hardware
    2. 3.2 Software
    3. 3.3 Application Software
      1. 3.3.1 Board and Peripherals Initialization (SYSCFG)
      2. 3.3.2 CPSW Configuration (ENET-LLD)
      3. 3.3.3 Operating System (FreeRTOS or NoRTOS)
      4. 3.3.4 Middleware Stack (LwIP, Arm® Mbed™ Platform TLS, TSN)
      5. 3.3.5 Application Layer
  7. 4Debugging Hardware and Software
    1. 4.1 Hardware Debugging
      1. 4.1.1 Schematic Review Checklist
        1. 4.1.1.1 Management Data Input/Output (MDIO and MDC)
        2. 4.1.1.2 RGMII Interface
      2. 4.1.2 PHY Debug
        1. 4.1.2.1 PHY Bootstrap Settings
        2. 4.1.2.2 Trace Length
        3. 4.1.2.3 Clock Configuration
        4. 4.1.2.4 Mode Settings
        5. 4.1.2.5 IO MUX and SW Switch Settings
        6. 4.1.2.6 PHY Troubleshooting Guides
        7. 4.1.2.7 Custom Pin MUX Settings
      3. 4.1.3 Test Setup
      4. 4.1.4 Software Debugging
        1. 4.1.4.1 Using GEL Scripts in CCS
          1. 4.1.4.1.1 Statistics Using GEL Scripts
          2. 4.1.4.1.2 Statistics Using Expressions
      5. 4.1.5 Debugging Custom Ethernet Software
        1. 4.1.5.1 Debugging Initialization Sequence
        2. 4.1.5.2 PHY Debugging
        3. 4.1.5.3 MAC Port Debugging
        4. 4.1.5.4 TX Path Debugging
        5. 4.1.5.5 Systematic Debugging Checklist
          1. 4.1.5.5.1 RX Path Debugging
          2. 4.1.5.5.2 Multicast or Broadcast Does Not Work, But Unicast Works
    2. 4.2 Custom Hardware Bring-Up Process
      1. 4.2.1 Example 1: CPSW PHY Loopback
        1. 4.2.1.1 Failure: PHY Not Detected or MDIO Bus Not Alive
        2. 4.2.1.2 Failure: TX Packets Transmitted But RX Count = 0
      2. 4.2.2 Example 2: CPSW MAC Loopback Example
        1. 4.2.2.1 Failure: MAC Loopback Initialization Fails
        2. 4.2.2.2 Failure: TX Packets Increase But RX = 0
        3. 4.2.2.3 Failure: Nonzero Error Counters
      3. 4.2.3 Example 3: Enet_Layer2_CPSW and Enet_Layer2_cpsw_switch
        1. 4.2.3.1 Hardware Setup
        2. 4.2.3.2 Failure: Link Never Comes UP
        3. 4.2.3.3 Failure: Link is Up But No Frames Are Received or Transmitted
        4. 4.2.3.4 Failure: RX and TX Counters Increase But Error Rates Are High
      4. 4.2.4 Example 4: Enet_lwip_cpsw_example
        1. 4.2.4.1 Failure: Link Never Comes Up
        2. 4.2.4.2 Failure: Links Up But No IP Address Is Assigned
        3. 4.2.4.3 Failure: Ping Fails Despite Link and IP Address
    3. 4.3 Debugging Packet Forwarding Issues (ALE and Statistics)
      1. 4.3.1 CPSW Statistics Architecture
        1. 4.3.1.1 What Each Block Measures
        2. 4.3.1.2 Counter Reference Tables
          1. 4.3.1.2.1 MAC Port – RX Counters
          2. 4.3.1.2.2 MAC Port – TX Counters
          3. 4.3.1.2.3 MAC Port and Host Port – ALE and FIFO Drop Counters
          4. 4.3.1.2.4 Host Port – ALE Flood and Overrun Counters
          5. 4.3.1.2.5 MAC Port RX Issues
          6. 4.3.1.2.6 MAC Port TX Issues
          7. 4.3.1.2.7 Host Port RX Issues
          8. 4.3.1.2.8 Host Port TX Issues
    4. 4.4 Custom Board Enablement in SYSCFG
    5. 4.5 LwIP Debug Guide
      1. 4.5.1 LwIP Stack Configuration
      2. 4.5.2 lwip_stats
  8. 5Conclusion
  9. 6References
4.3.1.2.5 MAC Port RX Issues

Table 4-17 highlights some issue that can be uncovered by the counter in the MAC port RX path. The counter name, debug method, and fix is mentioned in the table.

Table 4-17 MAC Port RX Statistical Summary
Scenario Nonzero Counter Root Cause Debug Method Fix | Reference
No frames from the PHY; link LED active rxGoodFrames = 0 The PHY is not linked, cable fault, or MDIO misconfiguration. Read ENET_MDIO_IOCTL_IS_ALIVE. Check the PHY address. PHY or Link Debug
Frames arrive but data is corrupted rxCrcErrors Cable noise, EMI, bad connector, or far-end duplex mismatch. Replace the cable. Read negotiated duplex using ENET_PHY_IOCTL_GET_LINK_STATUS. Force full-duplex using userLinkCaps in EnetPhy_Cfg
Signal errors, unreliable link rxAlignCodeErrors 8b/10b symbol error or non-octet-aligned frame – signal integrity. Shorten the cable. Check for EMI sources. Replace cable
All RX frames are dropped, CPU receives nothing aleBlockDrop The state of the ALE port 1 is BLOCKED or DISABLED – not set to FORWARD after initialization. Issue CPSW_ALE_IOCTL_GET_PORT_STATE for port 1. Set to FORWARD: CPSW_ALE_IOCTL_SET_PORT_STATE
Frames tagged as VLAN are silently dropped aleVidIngressDrop The 802.1Q VID in the frame is not registered in the ALE VLAN table for port 1. Dump the ALE table: CPSW_ALE_IOCTL_DUMP_TABLE. Check for VID entry with port 1. Add entry: CPSW_ALE_IOCTL_ADD_VLAN
Frames arrive, none reach the host port; no aleDrop portMaskDrop The ALE DA lookup succeeded but host port 0 is excluded from the egress portmask. Inspect the DA entry portmask using CPSW_ALE_IOCTL_DUMP_TABLE. Re-add DA entry with portmask including bit 0: CPSW_ALE_IOCTL_ADD_UCAST
Known source MAC is dropped; other traffic is OK aleSecureDrop The SA registered in the ALE with a secure flag on a different port. Find the SA entry in the ALE table dump. Check the portNum and secure fields. Delete stale entry: CPSW_ALE_IOCTL_DEL_UCAST; re-add without secure flag
Burst loss under high traffic aleOverrunDrop The burst rate exceeded the look-up FIFO capacity of the ALE. Monitor aleOverrunDrop delta over 1s under load. Configure ALE rate limiter: CPSW_ALE_IOCTL_SET_PORT_BCAST_MCAST_LIMIT