High-speed signals should be routed over a solid GND reference plane and not across a plane split or a void in the reference plane unless absolutely necessary. TI does not recommend high-speed signal references to power planes.

Routing across a plane split or a void in the reference plane forces return high-frequency current to flow around the split or void. This can result in the following conditions:

• Excess radiated emissions from an unbalanced current flow
• Delays in signal propagation delays due to increased series inductance
• Interference with adjacent signals
• Degraded signal integrity (that is, more jitter and reduced signal amplitude)

For examples of correct and incorrect plane void routing, see #SPRAAR7919 and #SPRAAR75896.

If routing over a plane-split is completely unavoidable, place stitching capacitors across the split to provide a return path for the high-frequency current. These stitching capacitors minimize the current loop area and any impedance discontinuity created by crossing the split. These capacitors should be 1 µF or lower and placed as close as possible to the plane crossing. For examples of incorrect plane-split routing and correct stitch capacitor placement, see #SPRAAR76296 and #SPRAAR79964.

When planning a PCB stackup, ensure that planes that do not reference each other are not overlapped because this produces unwanted capacitance between the overlapping areas. To see an example of how this capacitance could pass RF emissions from one plane to the other, see #SPRAAR71342.

The entirety of any high-speed signal trace should maintain the same GND reference from origination to termination. If unable to maintain the same GND reference, via-stitch both GND planes together to ensure continuous grounding and uniform impedance. Place these stitching vias symmetrically within 200 mils (center-to-center, closer is better) of the signal transition vias. For an example of stitching vias, see #SPRAAR7481.