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  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Scope
    2. 1.2 Critical Signals
  4. 2General High-Speed Signal Routing
    1. 2.1 PCB Fiber Weave Mitigation
    2. 2.2 High-Speed Signal Trace Lengths
    3. 2.3 High-Speed Signal Trace Length Matching
    4. 2.4 High-Speed Signal Reference Planes
  5. 3High-Speed Differential Signal Routing
    1. 3.1  Differential Signal Spacing
    2. 3.2  High-Speed Differential Signal Rules
    3. 3.3  Symmetry in the Differential Pairs
    4. 3.4  Crosstalk Between the Differential Signal Pairs
    5. 3.5  Connectors and Receptacles
    6. 3.6  Via Discontinuity Mitigation
    7. 3.7  Back-Drill Stubs
    8. 3.8  Increase Via Anti-Pad Diameter
    9. 3.9  Equalize Via Count
    10. 3.10 Surface-Mount Device Pad Discontinuity Mitigation
    11. 3.11 Signal Bending
    12. 3.12 Suggested PCB Stackups
    13. 3.13 ESD/EMI Considerations
    14. 3.14 ESD/EMI Layout Rules
  6. 4References
  7.   A Device Layout Parameters
  8.   Revision History

3.2 High-Speed Differential Signal Rules

  • Do not place probe or test points on any high-speed differential signal.
  • Do not route high-speed traces under or near crystals, oscillators, clock signal generators, switching power regulators, mounting holes, magnetic devices, or ICs that use or duplicate clock signals.
  • After BGA breakout, keep high-speed differential signals clear of the SoC because high current transients produced during internal state transitions can be difficult to filter out.
  • When possible, route high-speed differential pair signals on the top or bottom layer of the PCB with an adjacent GND layer. TI does not recommend stripline routing of the high-speed differential signals.
  • Ensure that high-speed differential signals are routed ≥ 90 mils from the edge of the reference plane.
  • Ensure that high-speed differential signals are routed at least 1.5 W (calculated trace-width × 1.5) away from voids in the reference plane. This rule does not apply where SMD pads on high-speed differential signals are voided.
  • Maintain constant trace width after the SoC BGA escape to avoid impedance mismatches in the transmission lines.
  • Maximize differential pair-to-pair spacing when possible.