Product details

Function Ultra-low jitter clock generator Number of outputs 8 Output frequency (Max) (MHz) 1000 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3, 2.5, 1.8 Input type CML, LVDS, LVPECL, XTAL Output type CML, HCSL, LVCMOS, LVDS, LVPECL Operating temperature range (C) -40 to 85 Features Integrated EEPROM, I2C, Pin programmable Rating Catalog
Function Ultra-low jitter clock generator Number of outputs 8 Output frequency (Max) (MHz) 1000 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3, 2.5, 1.8 Input type CML, LVDS, LVPECL, XTAL Output type CML, HCSL, LVCMOS, LVDS, LVPECL Operating temperature range (C) -40 to 85 Features Integrated EEPROM, I2C, Pin programmable Rating Catalog
WQFN (RHS) 48 49 mm² 7 x 7
  • Ultra Low Noise, High Performance
    • Jitter: 100-fs RMS Typical, FOUT > 100 MHz
    • PSNR: –80 dBc, Robust Supply Noise Immunity
  • Flexible Device Options
    • Up to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL or LVCMOS Outputs, or Any Combination
    • Pin Mode, I2C Mode, and EEPROM Mode
    • 71-Pin Selectable Pre-Programmed Default Start-Up Options
  • Dual Inputs With Automatic or Manual Selection
    • Crystal Input: 10 to 52 MHz
    • External Input: 1 to 300 MHz
  • Frequency Margining Options
    • Fine Frequency Margining (±50 ppm Typical) Using Low-Cost Pullable Crystal Reference
    • Glitchless Coarse Frequency Margining (%) Using Output Dividers
  • Other Features
    • Supply: 3.3-V Core, 1.8-V, 2.5-V, 3.3-V Output Supply
    • Industrial Temperature Range (–40ºC to +85ºC)
    • Package: 7-mm × 7-mm 48-WQFN
  • Ultra Low Noise, High Performance
    • Jitter: 100-fs RMS Typical, FOUT > 100 MHz
    • PSNR: –80 dBc, Robust Supply Noise Immunity
  • Flexible Device Options
    • Up to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL or LVCMOS Outputs, or Any Combination
    • Pin Mode, I2C Mode, and EEPROM Mode
    • 71-Pin Selectable Pre-Programmed Default Start-Up Options
  • Dual Inputs With Automatic or Manual Selection
    • Crystal Input: 10 to 52 MHz
    • External Input: 1 to 300 MHz
  • Frequency Margining Options
    • Fine Frequency Margining (±50 ppm Typical) Using Low-Cost Pullable Crystal Reference
    • Glitchless Coarse Frequency Margining (%) Using Output Dividers
  • Other Features
    • Supply: 3.3-V Core, 1.8-V, 2.5-V, 3.3-V Output Supply
    • Industrial Temperature Range (–40ºC to +85ºC)
    • Package: 7-mm × 7-mm 48-WQFN

The LMK03328 device is an ultra-low-noise clock generator with two fractional-N frequency synthesizers with integrated VCOs, flexible clock distribution and fanout, and pin-selectable configuration states stored in on-chip EEPROM. The device can generate multiple clocks for various multi-gigabit serial interfaces and digital devices, reduces BOM cost and board area, and improves reliability by replacing multiple oscillators and clock distribution devices. The ultra-low-jitter reduces bit error rate (BER) in high-speed serial links.

For each PLL, a differential/single-ended clock or crystal input can be selected as the PLL reference clock. The selected PLL reference input can be used to lock the VCO frequency at an integer or fractional multiple of the reference input frequency. The VCO frequency for the respective PLLs can be tuned between 4.8 GHz and 5.4 GHz. Both PLL/VCOs are equivalent in performance and functionality. Each PLL offers the flexibility to select a predefined or user-defined loop bandwidth, depending on the needs of the application. Each PLL has a post-divider that can be selected between divide-by 2, 3, 4, 5, 6, 7, or 8.

All the output channels can select the divided-down VCO clock from PLL1 or PLL2 as the source for the output divider to set the final output frequency. Some output channels can also independently select the reference input for PLL1 or PLL2 as an alternative source to be bypassed to the corresponding output buffers. The 8-bit output dividers support a divide range of 1 to 256 (even or odd), output frequencies up to 1 GHz, and output phase synchronization capability.

All output pairs are ground-referenced CML drivers with programmable swing that can be interfaced to LVDS or LVPECL or CML receivers with AC coupling. All output pairs can also be independently configured as HCSL outputs or 2x 1.8-V LVCMOS outputs. The outputs offer lower power at 1.8 V, higher performance and power supply noise immunity, and lower EMI compared to voltage-referenced driver designs (such as traditional LVDS and LVPECL drivers). Two additional 3.3-V LVCMOS outputs can be obtained through the STATUS pins. This is an optional feature in case of a need for 3.3-V LVCMOS outputs and device status signals are not needed.

The device features self start-up from on-chip programmable EEPROM or pre-defined ROM memory, which offers multiple custom device modes selectable through pin control and can eliminate the need for serial programming. The device registers and on-chip EEPROM settings are fully programmable via I2C-compatible serial interface. The device slave address is programmable in EEPROM and LSBs are settable with a 3-state pin.

The device provides two frequency margining options with glitch-free operation to support system design verification tests (DVT), such as standard compliance and system timing margin testing. Fine frequency margining (in ppm) can be supported by using a low-cost pullable crystal on the internal crystal oscillator (XO), and selecting this input as the reference to the PLL synthesizer. The frequency margining range is determined by the crystal’s trim sensitivity and the on-chip varactor range. XO frequency margining can be controlled through pin or I2C control for ease-of-use and high flexibility. Coarse frequency margining (in %) is available on any output channel by changing the output divide value through I2C interface, which synchronously stops and restarts the output clock to prevent a glitch or runt pulse when the divider is changed.

Internal power conditioning provide excellent power supply noise rejection (PSNR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from 3.3-V ± 5% supply and output blocks operate from 1.8-V, 2.5-V, 3.3-V ± 5% supply.

The LMK03328 device is an ultra-low-noise clock generator with two fractional-N frequency synthesizers with integrated VCOs, flexible clock distribution and fanout, and pin-selectable configuration states stored in on-chip EEPROM. The device can generate multiple clocks for various multi-gigabit serial interfaces and digital devices, reduces BOM cost and board area, and improves reliability by replacing multiple oscillators and clock distribution devices. The ultra-low-jitter reduces bit error rate (BER) in high-speed serial links.

For each PLL, a differential/single-ended clock or crystal input can be selected as the PLL reference clock. The selected PLL reference input can be used to lock the VCO frequency at an integer or fractional multiple of the reference input frequency. The VCO frequency for the respective PLLs can be tuned between 4.8 GHz and 5.4 GHz. Both PLL/VCOs are equivalent in performance and functionality. Each PLL offers the flexibility to select a predefined or user-defined loop bandwidth, depending on the needs of the application. Each PLL has a post-divider that can be selected between divide-by 2, 3, 4, 5, 6, 7, or 8.

All the output channels can select the divided-down VCO clock from PLL1 or PLL2 as the source for the output divider to set the final output frequency. Some output channels can also independently select the reference input for PLL1 or PLL2 as an alternative source to be bypassed to the corresponding output buffers. The 8-bit output dividers support a divide range of 1 to 256 (even or odd), output frequencies up to 1 GHz, and output phase synchronization capability.

All output pairs are ground-referenced CML drivers with programmable swing that can be interfaced to LVDS or LVPECL or CML receivers with AC coupling. All output pairs can also be independently configured as HCSL outputs or 2x 1.8-V LVCMOS outputs. The outputs offer lower power at 1.8 V, higher performance and power supply noise immunity, and lower EMI compared to voltage-referenced driver designs (such as traditional LVDS and LVPECL drivers). Two additional 3.3-V LVCMOS outputs can be obtained through the STATUS pins. This is an optional feature in case of a need for 3.3-V LVCMOS outputs and device status signals are not needed.

The device features self start-up from on-chip programmable EEPROM or pre-defined ROM memory, which offers multiple custom device modes selectable through pin control and can eliminate the need for serial programming. The device registers and on-chip EEPROM settings are fully programmable via I2C-compatible serial interface. The device slave address is programmable in EEPROM and LSBs are settable with a 3-state pin.

The device provides two frequency margining options with glitch-free operation to support system design verification tests (DVT), such as standard compliance and system timing margin testing. Fine frequency margining (in ppm) can be supported by using a low-cost pullable crystal on the internal crystal oscillator (XO), and selecting this input as the reference to the PLL synthesizer. The frequency margining range is determined by the crystal’s trim sensitivity and the on-chip varactor range. XO frequency margining can be controlled through pin or I2C control for ease-of-use and high flexibility. Coarse frequency margining (in %) is available on any output channel by changing the output divide value through I2C interface, which synchronously stops and restarts the output clock to prevent a glitch or runt pulse when the divider is changed.

Internal power conditioning provide excellent power supply noise rejection (PSNR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from 3.3-V ± 5% supply and output blocks operate from 1.8-V, 2.5-V, 3.3-V ± 5% supply.

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Technical documentation

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Type Title Date
* Data sheet LMK03328 Ultra-Low Jitter Clock Generator With Two Independent PLLs, Eight Outputs, Integrated EEPROM datasheet (Rev. D) 20 Apr 2018
Technical article Clock tree fundamentals: finding the right clocking devices for your design 24 Mar 2021
Application note Clocking for Medical Ultrasound Systems (Rev. A) 30 Sep 2020
Technical article Can a clock generator act as a jitter cleaner? 23 Mar 2017
Technical article The five benefits of multifaceted clocking devices 17 May 2016
Technical article Complete clock-tree solutions that make a hardware designer’s life easier 10 Mar 2016
Application note Clocking High Speed Serial Links with LMK033X8 (Rev. A) 07 Jan 2016
Application note Frequency Margining Using TI High-Performance Clock Generators (Rev. A) 12 Dec 2015
User guide LMK03328EVM CodeLoader Software User's Guide 25 Aug 2015
User guide LMK03328EVM User's Guide 25 Aug 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK03328EVM — LMK03328EVM Ultra-Low-Jitter Clock Generator EVM With 2 PLLs, 8 Differential Outputs, and 2 Inputs

The LMK03328EVM evaluation module provides a complete clocking platform to evaluate the 100-fs RMS jitter performance and pin-/software-configuration modes and features of the Texas Instruments LMK03328 Ultra-Low-Jitter Clock Generator with Dual PLLs, 8 outputs, 2 inputs, and integrated EEPROM.

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Application software & framework

TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software

The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
Software programming tool

LMK03328EVM Default EEPROM Image File

SNAC069.ZIP (2 KB)
Simulation model

LMK03328 IBIS Model (Rev. B)

SNAM177B.ZIP (88 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Package Pins Download
WQFN (RHS) 48 View options

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