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LMK03328

ACTIVE

Ultra-low jitter clock generator family with two independent PLLs

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Data sheet

LMK03328

ACTIVE
Data sheet Order now

Product details

Number of outputs 8 Output type CML, HCSL, LVCMOS, LVDS, LVPECL Output frequency (max) (MHz) 1000 Core supply voltage (V) 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type CML, LVDS, LVPECL, XTAL Operating temperature range (°C) -40 to 85 Features I2C, Integrated EEPROM, Pin programmable Rating Catalog
Number of outputs 8 Output type CML, HCSL, LVCMOS, LVDS, LVPECL Output frequency (max) (MHz) 1000 Core supply voltage (V) 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type CML, LVDS, LVPECL, XTAL Operating temperature range (°C) -40 to 85 Features I2C, Integrated EEPROM, Pin programmable Rating Catalog
WQFN (RHS) 48 49 mm² 7 x 7
  • Ultra-low noise, high performance
    • Jitter: 100fs RMS typical, FOUT > 100MHz
    • PSNR: –80dBc, robust supply noise immunity
  • Flexible device options
    • Up to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL or LVCMOS outputs, or any combination
    • Pin mode, I2C mode, and EEPROM mode
    • 71-pin selectable pre-programmed default start-up options
  • Dual inputs with automatic or manual selection
    • Crystal input: 10MHz to 52MHz
    • External input: 1MHz to 300MHz
  • Frequency margining options
    • Fine frequency margining (±50ppm typical) using low-cost pullable crystal reference
    • Glitchless coarse frequency margining (%) using output dividers
  • Other features
    • Supply: 3.3V core, 1.8V, 2.5V, 3.3V output
    • Industrial temperature range (–40°C to 85°C)
    • Package: 7mm × 7mm 48-WQFN
  • Ultra-low noise, high performance
    • Jitter: 100fs RMS typical, FOUT > 100MHz
    • PSNR: –80dBc, robust supply noise immunity
  • Flexible device options
    • Up to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL or LVCMOS outputs, or any combination
    • Pin mode, I2C mode, and EEPROM mode
    • 71-pin selectable pre-programmed default start-up options
  • Dual inputs with automatic or manual selection
    • Crystal input: 10MHz to 52MHz
    • External input: 1MHz to 300MHz
  • Frequency margining options
    • Fine frequency margining (±50ppm typical) using low-cost pullable crystal reference
    • Glitchless coarse frequency margining (%) using output dividers
  • Other features
    • Supply: 3.3V core, 1.8V, 2.5V, 3.3V output
    • Industrial temperature range (–40°C to 85°C)
    • Package: 7mm × 7mm 48-WQFN

The LMK03328 device is an ultra-low-noise clock generator that has two fractional-N frequency synthesizers with integrated VCOs, flexible clock distribution and fan-out, and pin-selectable configuration states stored in an on-chip EEPROM. The device can generate multiple clocks for various multi-gigabit serial interfaces and digital devices, which can reduce the BOM cost and board area, and can improve reliability by replacing multiple oscillators and clock distribution devices. The ultra-low-jitter reduces bit error rate (BER) in high-speed serial links.

The LMK03328 device is an ultra-low-noise clock generator that has two fractional-N frequency synthesizers with integrated VCOs, flexible clock distribution and fan-out, and pin-selectable configuration states stored in an on-chip EEPROM. The device can generate multiple clocks for various multi-gigabit serial interfaces and digital devices, which can reduce the BOM cost and board area, and can improve reliability by replacing multiple oscillators and clock distribution devices. The ultra-low-jitter reduces bit error rate (BER) in high-speed serial links.
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Technical documentation

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* Data sheet LMK03328 Ultra-Low Jitter Clock Generator With Two Independent PLLs, Eight Outputs, Integrated EEPROM datasheet (Rev. E) PDF | HTML 17 Sep 2024
Application note Clocking for PCIe Applications PDF | HTML 28 Nov 2023
Technical article Clock tree fundamentals: finding the right clocking devices for your design PDF | HTML 24 Mar 2021
Application note Clocking for Medical Ultrasound Systems (Rev. A) PDF | HTML 30 Sep 2020
Technical article Can a clock generator act as a jitter cleaner? PDF | HTML 23 Mar 2017
Technical article The five benefits of multifaceted clocking devices PDF | HTML 17 May 2016
Technical article Complete clock-tree solutions that make a hardware designer’s life easier PDF | HTML 10 Mar 2016
Application note Clocking High Speed Serial Links with LMK033X8 (Rev. A) 07 Jan 2016
Application note Frequency Margining Using TI High-Performance Clock Generators (Rev. A) 12 Dec 2015
Technical article How to select an optimal clocking solution for your FPGA-based design PDF | HTML 09 Dec 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK03328EVM — LMK03328EVM Ultra-Low-Jitter Clock Generator EVM With 2 PLLs, 8 Differential Outputs, and 2 Inputs

The LMK03328EVM evaluation module provides a complete clocking platform to evaluate the 100-fs RMS jitter performance and pin-/software-configuration modes and features of the Texas Instruments LMK03328 Ultra-Low-Jitter Clock Generator with Dual PLLs, 8 outputs, 2 inputs, and integrated EEPROM.

The (...)

User guide: PDF
Not available on TI.com
Software programming tool

SNAC069 — LMK03328EVM Default EEPROM Image File

Supported products & hardware

Supported products & hardware
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Support software

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

Supported products & hardware

Supported products & hardware
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Simulation model

LMK03328 IBIS Model (Rev. B)

SNAM177B.ZIP (88 KB) - IBIS Model
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Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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Design tool

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware

Supported products & hardware
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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WQFN (RHS) 48 Ultra Librarian
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