Home Clocks & timing Clock jitter cleaners & synchronizers
Home
Clocks & timing
Clock jitter cleaners & synchronizers
NEW

LMK04832-SEP

ACTIVE

Radiation-tolerant, 30-krad, ultra-low-noise, 3.2-GHz 15-output JESD204C clock jitter cleaner

Order now
Data sheet

LMK04832-SEP

ACTIVE
Data sheet Order now

Product details

Function Dual-loop PLL, Ultra-low jitter clock generator Number of outputs 15 RMS jitter (fs) 54 Output frequency (max) (MHz) 3255 Input type HCSL, LVCMOS, LVCMOS (REF_CLK), LVDS, LVPECL, LVPECL (VCXO_CLK) Output type CML, HSDS, LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Features 0 Delay, Integrated VCO, JESD204B, Loss of signal detection, Manual/auto switch, Programmable Delay, SPI Rating Space Operating temperature range (°C) -55 to 125, 25 to 25 Number of input channels 3
Function Dual-loop PLL, Ultra-low jitter clock generator Number of outputs 15 RMS jitter (fs) 54 Output frequency (max) (MHz) 3255 Input type HCSL, LVCMOS, LVCMOS (REF_CLK), LVDS, LVPECL, LVPECL (VCXO_CLK) Output type CML, HSDS, LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Features 0 Delay, Integrated VCO, JESD204B, Loss of signal detection, Manual/auto switch, Programmable Delay, SPI Rating Space Operating temperature range (°C) -55 to 125, 25 to 25 Number of input channels 3
HTQFP (PAP) 64 144 mm² 12 x 12
  • VID#: V62/22612
    • Total ionizing dose 30 krad (ELDRS-free)
    • SEL immune >43 MeV × cm2/mg
    • SEFI immune >43 MeV × cm2/mg
  • Ambient temperature range: –55°C to 125°C
  • Maximum clock output frequency: 3255 MHz
  • Multi-mode: dual PLL, single PLL, and clock distribution
  • 6-GHz external VCO or distribution input
  • Ultra-low noise, at 2500 MHz:
    • 54-fs RMS jitter (12 kHz to 20 MHz)
    • 64-fs RMS jitter (100 Hz to 20 MHz)
    • –157.6-dBc/Hz noise floor
  • Ultra-low noise, at 3200 MHz:
    • 61-fs RMS jitter (12 kHz to 20 MHz)
    • 67-fs RMS jitter (100 Hz to 100 MHz)
    • –156.5-dBc/Hz noise floor
  • PLL2
    • PLL FOM of –230 dBc/Hz
    • PLL 1/f of –128 dBc/Hz
    • Phase detector rate up to 320 MHz
    • Two integrated VCOs: 2440 to 2600 MHz and 2945 to 3255 MHz
  • Up to 14 differential device clocks
    • CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS programmable outputs
  • Up to 1 buffered VCXO/XO output
    • LVPECL, LVDS, 2xLVCMOS programmable
  • 1-1023 CLKOUT divider
  • 1-8191 SYSREF divider
  • 25-ps step analog delay for SYSREF clocks
  • Digital delay and dynamic digital delay for device clocks and SYSREF
  • Holdover mode with PLL1
  • 0-delay with PLL1 or PLL2
  • High Reliability
    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability
  • VID#: V62/22612
    • Total ionizing dose 30 krad (ELDRS-free)
    • SEL immune >43 MeV × cm2/mg
    • SEFI immune >43 MeV × cm2/mg
  • Ambient temperature range: –55°C to 125°C
  • Maximum clock output frequency: 3255 MHz
  • Multi-mode: dual PLL, single PLL, and clock distribution
  • 6-GHz external VCO or distribution input
  • Ultra-low noise, at 2500 MHz:
    • 54-fs RMS jitter (12 kHz to 20 MHz)
    • 64-fs RMS jitter (100 Hz to 20 MHz)
    • –157.6-dBc/Hz noise floor
  • Ultra-low noise, at 3200 MHz:
    • 61-fs RMS jitter (12 kHz to 20 MHz)
    • 67-fs RMS jitter (100 Hz to 100 MHz)
    • –156.5-dBc/Hz noise floor
  • PLL2
    • PLL FOM of –230 dBc/Hz
    • PLL 1/f of –128 dBc/Hz
    • Phase detector rate up to 320 MHz
    • Two integrated VCOs: 2440 to 2600 MHz and 2945 to 3255 MHz
  • Up to 14 differential device clocks
    • CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS programmable outputs
  • Up to 1 buffered VCXO/XO output
    • LVPECL, LVDS, 2xLVCMOS programmable
  • 1-1023 CLKOUT divider
  • 1-8191 SYSREF divider
  • 25-ps step analog delay for SYSREF clocks
  • Digital delay and dynamic digital delay for device clocks and SYSREF
  • Holdover mode with PLL1
  • 0-delay with PLL1 or PLL2
  • High Reliability
    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability

The LMK04832-SEP is a high performance clock conditioner with JEDEC JESD204B/C support for space applications.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B/C converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B/C applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

This device can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.

The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover allows to provide flexible high performance clocking trees.

The LMK04832-SEP is a high performance clock conditioner with JEDEC JESD204B/C support for space applications.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B/C converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B/C applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

This device can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.

The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover allows to provide flexible high performance clocking trees.
open-in-new Find other Clock jitter cleaners & synchronizers
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare products
Similar functionality to the compared device.
LMK04832-SP ACTIVE Radiation-hardened-assured (RHA), ultra-low-noise, 3.2-GHz, 15-output clock jitter cleaner

3.2-GHz jitter cleaner with JESD204C support, 100-krad TID, and 120-MeV-cm2/mg for GEO missions

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 7
Type Title Date
* Data sheet LMK04832-SEP Space Grade Ultra-Low-Noise JESD204B/C Dual-Loop Clock Jitter Cleaner datasheet (Rev. A) PDF | HTML 07 Nov 2022
* Radiation & reliability report LMK04832-SEP TID RLAT Report 19 Nov 2022
* Radiation & reliability report LMK04832-SEP Process Flow and Reliability Report PDF | HTML 18 Nov 2022
* Radiation & reliability report LMK04832-SEP Single-Event Effects Report PDF | HTML 18 Nov 2022
More literature Multi-Clock Synchronization 30 Dec 2019
Analog Design Journal JESD204B multi-device synchronization: Breaking down the requirements 28 Apr 2015
Analog Design Journal When is the JESD204B interface the right choice? 22 Jan 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK04832SEPEVM — LMK04832-SEP evaluation module for ultra-low-noise, 3.2-GHz 15-output clock jitter clea

The LMK04832-SEP evaluation module (EVM) is a platform to evaluate the performance and features of the LMK04832-SEP, which is a space-grade, ultra-low-noise, JESD204B/C, dual-loop clock jitter cleaner.

The LMK04832-SEP device on each EVM is an engineering model, intended for engineering evaluation (...)

User guide: PDF | HTML
Not available on TI.com
Evaluation board

ALPHA-3P-ADM-VA600-SPACE-AMD — Alpha Data ADM-VA600 kit using AMD Versal core XQRVC1902 ACAP and TI radiation-tolerant products

This is a 6U VPX form factor highlighting the AMD-Xilinx® Versal AI Core XQRVC1902 adaptable SoC/FPGA. The ADM-VA600 is modular board design with one FMC+ connector, DDR4 DRAM and system monitoring. The majority of the components are radiation-tolerant power management, interface, clocking and (...)

From: Alpha Data Parallel Systems Ltd.
Go to third party
Application software & framework

PLLATINUMSIM-SW — Texas Instruments PLLatinum Simulator Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
Download
Application software & framework

TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
Download
Simulation model

LMK04832-SEP IBIS Model

SNAM259.ZIP (168 KB) - IBIS Model
Download
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Design now
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Package Pins Download
HTQFP (PAP) 64 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos