SPRSP65B April   2021  – July 2021 AM2431 , AM2432 , AM2434

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
    1. 3.1 Functional Block Diagram
  4. Revision History
  5. Device Comparison
    1. 5.1 Related Products
  6. Terminal Configuration and Functions
    1. 6.1 Pin Diagram
      1. 6.1.1 AM243x ALV Pin Diagram
      2. 6.1.2 AM243x ALX Pin Diagram
    2. 6.2 Pin Attributes (ALV Package)
    3. 6.3 Pin Attributes (ALX Package)
    4. 6.4 Signal Descriptions
      1. 6.4.1  ADC
        1.       MAIN Domain Instances
        2. 6.4.1.1 ADC0 Signal Descriptions
      2. 6.4.2  DDRSS
        1.       MAIN Domain Instances
        2. 6.4.2.1 DDRSS0 Signal Descriptions
      3. 6.4.3  GPIO
        1.       MAIN Domain Instances
        2. 6.4.3.1 GPIO0 Signal Descriptions
        3. 6.4.3.2 GPIO1 Signal Descriptions
        4.       MCU Domain Instances
        5. 6.4.3.3 MCU_GPIO0 Signal Descriptions
      4. 6.4.4  I2C
        1.       MAIN Domain Instances
        2. 6.4.4.1 I2C0 Signal Descriptions
        3. 6.4.4.2 I2C1 Signal Descriptions
        4. 6.4.4.3 I2C2 Signal Descriptions
        5. 6.4.4.4 I2C3 Signal Descriptions
        6.       MCU Domain Instances
        7. 6.4.4.5 MCU_I2C0 Signal Descriptions
        8. 6.4.4.6 MCU_I2C1 Signal Descriptions
      5. 6.4.5  MCAN
        1.       MAIN Domain Instances
        2. 6.4.5.1 MCAN0 Signal Descriptions
        3. 6.4.5.2 MCAN1 Signal Descriptions
      6. 6.4.6  SPI (MCSPI)
        1.       MAIN Domain Instances
        2. 6.4.6.1 MCSPI0 Signal Descriptions
        3. 6.4.6.2 MCSPI1 Signal Descriptions
        4. 6.4.6.3 MCSPI2 Signal Descriptions
        5. 6.4.6.4 MCSPI3 Signal Descriptions
        6. 6.4.6.5 MCSPI4 Signal Descriptions
        7.       MCU Domain Instances
        8. 6.4.6.6 MCU_MCSPI0 Signal Descriptions
        9. 6.4.6.7 MCU_MCSPI1 Signal Descriptions
      7. 6.4.7  UART
        1.       MAIN Domain Instances
        2. 6.4.7.1 UART0 Signal Descriptions
        3. 6.4.7.2 UART1 Signal Descriptions
        4. 6.4.7.3 UART2 Signal Descriptions
        5. 6.4.7.4 UART3 Signal Descriptions
        6. 6.4.7.5 UART4 Signal Descriptions
        7. 6.4.7.6 UART5 Signal Descriptions
        8. 6.4.7.7 UART6 Signal Descriptions
        9.       MCU Domain Instances
        10. 6.4.7.8 MCU_UART0 Signal Descriptions
        11. 6.4.7.9 MCU_UART1 Signal Descriptions
      8. 6.4.8  MDIO
        1.       MAIN Domain Instances
        2. 6.4.8.1 MDIO0 Signal Descriptions
      9. 6.4.9  CPSW
        1.       MAIN Domain Instances
        2. 6.4.9.1 CPSW3G0 Signal Descriptions
      10. 6.4.10 ECAP
        1.       MAIN Domain Instances
        2. 6.4.10.1 ECAP0 Signal Descriptions
        3. 6.4.10.2 ECAP1 Signal Descriptions
        4. 6.4.10.3 ECAP2 Signal Descriptions
      11.      EQEP
        1.       MAIN Domain Instances
        2. 6.4.11.1 EQEP0 Signal Descriptions
        3. 6.4.11.2 EQEP1 Signal Descriptions
        4. 6.4.11.3 EQEP2 Signal Descriptions
      12. 6.4.11 EPWM
        1.       MAIN Domain Instances
        2. 6.4.11.1  EPWM Signal Descriptions
        3. 6.4.11.2  EPWM0 Signal Descriptions
        4. 6.4.11.3  EPWM1 Signal Descriptions
        5. 6.4.11.4  EPWM2 Signal Descriptions
        6. 6.4.11.5  EPWM3 Signal Descriptions
        7. 6.4.11.6  EPWM4 Signal Descriptions
        8. 6.4.11.7  EPWM5 Signal Descriptions
        9. 6.4.11.8  EPWM6 Signal Descriptions
        10. 6.4.11.9  EPWM7 Signal Descriptions
        11. 6.4.11.10 EPWM8 Signal Descriptions
      13. 6.4.12 SERDES
        1.       MAIN Domain Instances
        2. 6.4.12.1 SERDES0 Signal Descriptions
      14. 6.4.13 USB
        1.       MAIN Domain Instances
        2. 6.4.13.1 USB0 Signal Descriptions
      15. 6.4.14 OSPI
        1.       MAIN Domain Instances
        2. 6.4.14.1 OSPI0 Signal Descriptions
      16. 6.4.15 GPMC
        1.       MAIN Domain Instances
        2. 6.4.15.1 GPMC0 Signal Descriptions
      17. 6.4.16 MMC
        1.       MAIN Domain Instances
        2. 6.4.16.1 MMC0 Signal Descriptions
        3. 6.4.16.2 MMC1 Signal Descriptions
      18. 6.4.17 FSITX
        1.       MAIN Domain Instances
        2. 6.4.17.1 FSI0 TX Signal Descriptions
        3. 6.4.17.2 FSI1 TX Signal Descriptions
      19. 6.4.18 FSIRX
        1.       MAIN Domain Instances
        2. 6.4.18.1 FSI0 RX Signal Descriptions
        3. 6.4.18.2 FSI1 RX Signal Descriptions
        4. 6.4.18.3 FSI2 RX Signal Descriptions
        5. 6.4.18.4 FSI3 RX Signal Descriptions
        6. 6.4.18.5 FSI4 RX Signal Descriptions
        7. 6.4.18.6 FSI5 RX Signal Descriptions
      20. 6.4.19 CPTS
        1.       MAIN Domain Instances
        2. 6.4.19.1 CPTS0 Signal Descriptions
        3. 6.4.19.2 CP GEMAC CPTS0 Signal Descriptions
      21. 6.4.20 ICSSG
        1.       MAIN Domain Instances
        2. 6.4.20.1 PRU_ICSSG0 Signal Descriptions
        3. 6.4.20.2 PRU_ICSSG1 Signal Descriptions
      22. 6.4.21 DMTIMER
        1.       MAIN Domain Instances
        2. 6.4.21.1 DMTIMER Signal Descriptions
        3.       MCU Domain Instances
        4. 6.4.21.2 MCU_DMTIMER Signal Descriptions
      23. 6.4.22 TRACE
        1.       MAIN Domain Instances
        2. 6.4.22.1 Trace Signal Descriptions
      24. 6.4.23 JTAG
        1.       MAIN Domain Instances
        2. 6.4.23.1 JTAG Signal Descriptions
      25. 6.4.24 SYSBOOT
        1.       MAIN Domain Instances
        2. 6.4.24.1 Sysboot Signal Descriptions
      26. 6.4.25 SYSTEM
        1.       MAIN Domain Instances
        2. 6.4.25.1 System Signal Descriptions
        3.       MCU Domain Instances
        4. 6.4.25.2 MCU System Signal Descriptions
      27. 6.4.26 CLOCK
        1.       MCU Domain Instances
        2. 6.4.26.1 MCU Clock Signal Descriptions
      28. 6.4.27 VMON
        1. 6.4.27.1 VMON Signal Description
      29. 6.4.28 Power Supply
        1. 6.4.28.1 Power Supply Signal Description
    5. 6.5 Pin Multiplexing
    6. 6.6 Connections for Unused Pins
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Operating Performance Points
    6. 7.6  Power Consumption Summary
    7. 7.7  Electrical Characteristics
      1. 7.7.1 Fail-Safe Reset (FS RESET) Electrical Characteristics
      2. 7.7.2 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      3. 7.7.3 High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 7.7.4 eMMCPHY Electrical Characteristics
      5. 7.7.5 SDIO Electrical Characteristics
      6. 7.7.6 ADC12B Electrical Characteristics
      7. 7.7.7 LVCMOS Electrical Characteristics
      8. 7.7.8 USB2PHY Electrical Characteristics
      9. 7.7.9 DDR Electrical Characteristics
    8. 7.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.8.2 Hardware Requirements
      3. 7.8.3 Programming Sequence
      4. 7.8.4 Impact to Your Hardware Warranty
    9. 7.9  Thermal Resistance Characteristics
      1. 7.9.1 Thermal Resistance Characteristics
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Sequencing
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Power-Up Sequencing
        3. 7.10.2.3 Power-Down Sequencing
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Safety Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input Clocks / Oscillators
          1. 7.10.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
      5. 7.10.5 Peripherals
        1. 7.10.5.1  CPSW3G
          1. 7.10.5.1.1 CPSW3G MDIO Timing
          2. 7.10.5.1.2 CPSW3G RMII Timing
          3. 7.10.5.1.3 CPSW3G RGMII Timing
        2. 7.10.5.2  DDRSS
        3. 7.10.5.3  ECAP
        4. 7.10.5.4  EPWM
        5. 7.10.5.5  EQEP
        6. 7.10.5.6  FSI
        7. 7.10.5.7  GPIO
        8. 7.10.5.8  GPMC
          1. 7.10.5.8.1 GPMC and NOR Flash — Synchronous Mode
          2. 7.10.5.8.2 GPMC and NOR Flash — Asynchronous Mode
          3. 7.10.5.8.3 GPMC and NAND Flash — Asynchronous Mode
        9. 7.10.5.9  I2C
          1. 7.10.5.9.1 Timing Requirements for I2C Input Timings
        10. 7.10.5.10 MCAN
        11. 7.10.5.11 MCSPI
          1. 7.10.5.11.1 MCSPI — Master Mode
          2. 7.10.5.11.2 MCSPI — Slave Mode
        12. 7.10.5.12 MMCSD
          1. 7.10.5.12.1 MMC0 - eMMC Interface
            1. 7.10.5.12.1.1 Legacy SDR Mode
            2. 7.10.5.12.1.2 High Speed SDR Mode
            3. 7.10.5.12.1.3 High Speed DDR Mode
            4. 7.10.5.12.1.4 HS200 Mode
          2. 7.10.5.12.2 MMC1 - SD/SDIO Interface
            1. 7.10.5.12.2.1 Default Speed Mode
            2. 7.10.5.12.2.2 High Speed Mode
            3. 7.10.5.12.2.3 UHS–I SDR12 Mode
            4. 7.10.5.12.2.4 UHS–I SDR25 Mode
            5. 7.10.5.12.2.5 UHS–I SDR50 Mode
            6. 7.10.5.12.2.6 UHS–I DDR50 Mode
            7. 7.10.5.12.2.7 UHS–I SDR104 Mode
        13. 7.10.5.13 CPTS
        14. 7.10.5.14 OSPI
          1. 7.10.5.14.1 OSPI With Data Training
            1. 7.10.5.14.1.1 OSPI Switching Characteristics – Data Training
          2. 7.10.5.14.2 OSPI Without Data Training
            1. 7.10.5.14.2.1 OSPI SDR Timing
            2. 7.10.5.14.2.2 OSPI DDR Timing
        15. 7.10.5.15 PCIe
        16. 7.10.5.16 PRU_ICSSG
          1. 7.10.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)
            1. 7.10.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing
            2. 7.10.5.16.1.2 PRU_ICSSG PRU Parallel Capture Mode Timing
            3. 7.10.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing
            4. 7.10.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface
              1. 7.10.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing
          2. 7.10.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 7.10.5.16.2.1 PRU_ICSSG PWM Timing
          3. 7.10.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)
            1. 7.10.5.16.3.1 PRU_ICSSG IEP Timing
          4. 7.10.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)
            1. 7.10.5.16.4.1 PRU_ICSSG UART Timing
          5. 7.10.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)
            1. 7.10.5.16.5.1 PRU_ICSSG ECAP Timing
          6. 7.10.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 7.10.5.16.6.1 PRU_ICSSG MDIO Timing
            2. 7.10.5.16.6.2 PRU_ICSSG MII Timing
            3. 7.10.5.16.6.3 PRU_ICSSG RGMII Timing
        17. 7.10.5.17 Timers
        18. 7.10.5.18 UART
        19. 7.10.5.19 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Trace
        2. 7.10.6.2 JTAG
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-R5F Subsystem (R5FSS)
      2. 8.2.2 Arm Cortex-M4F (M4FSS)
    3. 8.3 Accelerators and Coprocessors
      1. 8.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)
    4. 8.4 Other Subsystems
      1. 8.4.1 PDMA Controller
      2. 8.4.2 Peripherals
        1. 8.4.2.1  ADC
        2. 8.4.2.2  DCC
        3. 8.4.2.3  Dual Date Rate (DDR) External Memory Interface (DDRSS)
        4. 8.4.2.4  ECAP
        5. 8.4.2.5  EPWM
        6. 8.4.2.6  ELM
        7. 8.4.2.7  ESM
        8. 8.4.2.8  GPIO
        9. 8.4.2.9  EQEP
        10. 8.4.2.10 GPMC
        11. 8.4.2.11 I2C
        12. 8.4.2.12 MCAN
        13. 8.4.2.13 MCRC Controller
        14. 8.4.2.14 MCSPI
        15. 8.4.2.15 MMCSD
        16. 8.4.2.16 OSPI
        17. 8.4.2.17 Peripheral Component Interconnect Express (PCIe)
        18. 8.4.2.18 Serializer/Deserializer (SerDes)
        19. 8.4.2.19 RTI
        20. 8.4.2.20 DMTIMER
        21. 8.4.2.21 UART
        22. 8.4.2.22 Universal Serial Bus Subsystem(USBSS)
  9. Applications, Implementation, and Layout
    1. 9.1 Power Supply Mapping
    2. 9.2 Device Connection and Layout Fundamentals
      1. 9.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.2.1.1 Power Distribution Network Implementation Guidance
      2. 9.2.2 External Oscillator
      3. 9.2.3 JTAG and EMU
      4. 9.2.4 Unused Pins
    3. 9.3 Peripheral- and Interface-Specific Design Information
      1. 9.3.1 General Routing Guidelines
      2. 9.3.2 DDR Board Design and Layout Guidelines
      3. 9.3.3 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.3.3.1 No Loopback and Internal Pad Loopback
        2. 9.3.3.2 External Board Loopback
        3. 9.3.3.3 DQS (only available in Octal Flash devices)
      4. 9.3.4 USB VBUS Design Guidelines
      5. 9.3.5 System Power Supply Monitor Design Guidelines
      6. 9.3.6 High Speed Differential Signal Routing Guidance
      7. 9.3.7 Thermal Solution Guidance
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALV|441
  • ALX|293
Thermal pad, mechanical data (Package|Pins)
Orderable Information

PRU_ICSSG1 Signal Descriptions

Table 6-67 PRU_ICSSG1 Signal Descriptions
SIGNAL
NAME
SIGNAL
TYPE
DESCRIPTIONALVALX
PRG1_ECAP0_IN_APWM_OUTIOPRU-ICSSG Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) OuputV12AA13
PRG1_ECAP0_SYNC_INIPRU-ICSSG ECAP Sync Input Y13Y15
PRG1_ECAP0_SYNC_OUTOPRU-ICSSG ECAP Sync OutputAA14AA14
PRG1_IEP0_EDIO_OUTVALIDOPRU_ICSSG Industrial Ethernet Digital I/O OutvalidD14
PRG1_IEP0_EDC_LATCH_IN0IPRU_ICSSG Industrial Ethernet Distributed Clock Latch InputV7Y4
PRG1_IEP0_EDC_LATCH_IN1IPRU_ICSSG Industrial Ethernet Distributed Clock Latch InputU13V13
PRG1_IEP0_EDC_SYNC_OUT0OPRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputW7U3
PRG1_IEP0_EDC_SYNC_OUT1OPRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputU7T2
PRG1_IEP0_EDIO_DATA_IN_OUT28IOPRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputU15W16
PRG1_IEP0_EDIO_DATA_IN_OUT29IOPRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputU14W13
PRG1_IEP0_EDIO_DATA_IN_OUT30IOPRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputV14Y16
PRG1_IEP0_EDIO_DATA_IN_OUT31IOPRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputW14U13
PRG1_IEP1_EDC_LATCH_IN0IPRU_ICSSG Industrial Ethernet Distributed Clock Latch InputY13Y15
PRG1_IEP1_EDC_LATCH_IN1IPRU_ICSSG Industrial Ethernet Distributed Clock Latch InputV15Y14
PRG1_IEP1_EDC_SYNC_OUT0OPRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputV12AA13
PRG1_IEP1_EDC_SYNC_OUT1OPRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputAA14AA14
PRG1_MDIO0_MDCOPRU-ICSSG MDIO ClockY6W1
PRG1_MDIO0_MDIOIOPRU-ICSSG MDIO DataAA6V2
PRG1_PRU0_GPI0IPRU-ICSSG PRU Data InputY7V4
PRG1_PRU0_GPI1IPRU-ICSSG PRU Data InputU8W5
PRG1_PRU0_GPI2IPRU-ICSSG PRU Data InputW8AA4
PRG1_PRU0_GPI3IPRU-ICSSG PRU Data InputV8Y5
PRG1_PRU0_GPI4IPRU-ICSSG PRU Data InputY8AA5
PRG1_PRU0_GPI5IPRU-ICSSG PRU Data InputV13U14
PRG1_PRU0_GPI6IPRU-ICSSG PRU Data InputAA7Y2
PRG1_PRU0_GPI7IPRU-ICSSG PRU Data InputU13V13
PRG1_PRU0_GPI8IPRU-ICSSG PRU Data InputW13Y13
PRG1_PRU0_GPI9IPRU-ICSSG PRU Data InputU15W16
PRG1_PRU0_GPI10IPRU-ICSSG PRU Data InputU14W13
PRG1_PRU0_GPI11IPRU-ICSSG PRU Data InputAA8V5
PRG1_PRU0_GPI12IPRU-ICSSG PRU Data InputU9W2
PRG1_PRU0_GPI13IPRU-ICSSG PRU Data InputW9V6
PRG1_PRU0_GPI14IPRU-ICSSG PRU Data InputAA9AA7
PRG1_PRU0_GPI15IPRU-ICSSG PRU Data InputY9Y7
PRG1_PRU0_GPI16IPRU-ICSSG PRU Data InputV9W6
PRG1_PRU0_GPI17IPRU-ICSSG PRU Data InputU7T2
PRG1_PRU0_GPI18IPRU-ICSSG PRU Data InputV7Y4
PRG1_PRU0_GPI19IPRU-ICSSG PRU Data InputW7U3
PRG1_PRU0_GPO0IOPRU-ICSSG PRU Data OutputY7V4
PRG1_PRU0_GPO1IOPRU-ICSSG PRU Data OutputU8W5
PRG1_PRU0_GPO2IOPRU-ICSSG PRU Data OutputW8AA4
PRG1_PRU0_GPO3IOPRU-ICSSG PRU Data OutputV8Y5
PRG1_PRU0_GPO4IOPRU-ICSSG PRU Data OutputY8AA5
PRG1_PRU0_GPO5IOPRU-ICSSG PRU Data OutputV13U14
PRG1_PRU0_GPO6IOPRU-ICSSG PRU Data OutputAA7Y2
PRG1_PRU0_GPO7IOPRU-ICSSG PRU Data OutputU13V13
PRG1_PRU0_GPO8IOPRU-ICSSG PRU Data OutputW13Y13
PRG1_PRU0_GPO9IOPRU-ICSSG PRU Data OutputU15W16
PRG1_PRU0_GPO10IOPRU-ICSSG PRU Data OutputU14W13
PRG1_PRU0_GPO11IOPRU-ICSSG PRU Data OutputAA8V5
PRG1_PRU0_GPO12IOPRU-ICSSG PRU Data OutputU9W2
PRG1_PRU0_GPO13IOPRU-ICSSG PRU Data OutputW9V6
PRG1_PRU0_GPO14IOPRU-ICSSG PRU Data OutputAA9AA7
PRG1_PRU0_GPO15IOPRU-ICSSG PRU Data OutputY9Y7
PRG1_PRU0_GPO16IOPRU-ICSSG PRU Data OutputV9W6
PRG1_PRU0_GPO17IOPRU-ICSSG PRU Data OutputU7T2
PRG1_PRU0_GPO18IOPRU-ICSSG PRU Data OutputV7Y4
PRG1_PRU0_GPO19IOPRU-ICSSG PRU Data OutputW7U3
PRG1_PRU1_GPI0IPRU-ICSSG PRU Data InputW11AA10
PRG1_PRU1_GPI1IPRU-ICSSG PRU Data InputV11Y10
PRG1_PRU1_GPI2IPRU-ICSSG PRU Data InputAA12Y11
PRG1_PRU1_GPI3IPRU-ICSSG PRU Data InputY12V12
PRG1_PRU1_GPI4IPRU-ICSSG PRU Data InputW12Y12
PRG1_PRU1_GPI5IPRU-ICSSG PRU Data InputAA13AA11
PRG1_PRU1_GPI6IPRU-ICSSG PRU Data InputU11V10
PRG1_PRU1_GPI7IPRU-ICSSG PRU Data InputV15Y14
PRG1_PRU1_GPI8IPRU-ICSSG PRU Data InputU12W11
PRG1_PRU1_GPI9IPRU-ICSSG PRU Data InputV14Y16
PRG1_PRU1_GPI10IPRU-ICSSG PRU Data InputW14U13
PRG1_PRU1_GPI11IPRU-ICSSG PRU Data InputAA10Y6
PRG1_PRU1_GPI12IPRU-ICSSG PRU Data InputV10AA8
PRG1_PRU1_GPI13IPRU-ICSSG PRU Data InputU10Y9
PRG1_PRU1_GPI14IPRU-ICSSG PRU Data InputAA11W9
PRG1_PRU1_GPI15IPRU-ICSSG PRU Data InputY11V9
PRG1_PRU1_GPI16IPRU-ICSSG PRU Data InputY10Y8
PRG1_PRU1_GPI17IPRU-ICSSG PRU Data InputAA14AA14
PRG1_PRU1_GPI18IPRU-ICSSG PRU Data InputY13Y15
PRG1_PRU1_GPI19IPRU-ICSSG PRU Data InputV12AA13
PRG1_PRU1_GPO0IOPRU-ICSSG PRU Data OutputW11AA10
PRG1_PRU1_GPO1IOPRU-ICSSG PRU Data OutputV11Y10
PRG1_PRU1_GPO2IOPRU-ICSSG PRU Data OutputAA12Y11
PRG1_PRU1_GPO3IOPRU-ICSSG PRU Data OutputY12V12
PRG1_PRU1_GPO4IOPRU-ICSSG PRU Data OutputW12Y12
PRG1_PRU1_GPO5IOPRU-ICSSG PRU Data OutputAA13AA11
PRG1_PRU1_GPO6IOPRU-ICSSG PRU Data OutputU11V10
PRG1_PRU1_GPO7IOPRU-ICSSG PRU Data OutputV15Y14
PRG1_PRU1_GPO8IOPRU-ICSSG PRU Data OutputU12W11
PRG1_PRU1_GPO9IOPRU-ICSSG PRU Data OutputV14Y16
PRG1_PRU1_GPO10IOPRU-ICSSG PRU Data OutputW14U13
PRG1_PRU1_GPO11IOPRU-ICSSG PRU Data OutputAA10Y6
PRG1_PRU1_GPO12IOPRU-ICSSG PRU Data OutputV10AA8
PRG1_PRU1_GPO13IOPRU-ICSSG PRU Data OutputU10Y9
PRG1_PRU1_GPO14IOPRU-ICSSG PRU Data OutputAA11W9
PRG1_PRU1_GPO15IOPRU-ICSSG PRU Data OutputY11V9
PRG1_PRU1_GPO16IOPRU-ICSSG PRU Data OutputY10Y8
PRG1_PRU1_GPO17IOPRU-ICSSG PRU Data OutputAA14AA14
PRG1_PRU1_GPO18IOPRU-ICSSG PRU Data OutputY13Y15
PRG1_PRU1_GPO19IOPRU-ICSSG PRU Data OutputV12AA13
PRG1_PWM0_TZ_INIPRU_ICSSG PWM Trip Zone InputV7Y4
PRG1_PWM0_TZ_OUTOPRU_ICSSG PWM Trip Zone OutputW7U3
PRG1_PWM1_TZ_INIPRU_ICSSG PWM Trip Zone InputY13Y15
PRG1_PWM1_TZ_OUTOPRU_ICSSG PWM Trip Zone OutputV12AA13
PRG1_PWM2_TZ_INIPRU_ICSSG PWM Trip Zone InputP19, W14U13
PRG1_PWM2_TZ_OUTOPRU_ICSSG PWM Trip Zone OutputR20, U12W11
PRG1_PWM3_TZ_INIPRU_ICSSG PWM Trip Zone InputU15W16
PRG1_PWM3_TZ_OUTOPRU_ICSSG PWM Trip Zone OutputAA8V5
PRG1_PWM0_A0IOPRU_ICSSG PWM Output AU9W2
PRG1_PWM0_A1IOPRU_ICSSG PWM Output AAA9AA7
PRG1_PWM0_A2IOPRU_ICSSG PWM Output AV9W6
PRG1_PWM0_B0IOPRU_ICSSG PWM Output BW9V6
PRG1_PWM0_B1IOPRU_ICSSG PWM Output BY9Y7
PRG1_PWM0_B2IOPRU_ICSSG PWM Output BU7T2
PRG1_PWM1_A0IOPRU_ICSSG PWM Output AV10AA8
PRG1_PWM1_A1IOPRU_ICSSG PWM Output AAA11W9
PRG1_PWM1_A2IOPRU_ICSSG PWM Output AY10Y8
PRG1_PWM1_B0IOPRU_ICSSG PWM Output BU10Y9
PRG1_PWM1_B1IOPRU_ICSSG PWM Output BY11V9
PRG1_PWM1_B2IOPRU_ICSSG PWM Output BAA14AA14
PRG1_PWM2_A0IOPRU_ICSSG PWM Output AN16, W8AA4
PRG1_PWM2_A1IOPRU_ICSSG PWM Output AP17, W13Y13
PRG1_PWM2_A2IOPRU_ICSSG PWM Output AAA12, V21U19, Y11
PRG1_PWM2_B0IOPRU_ICSSG PWM Output BN17, Y8AA5
PRG1_PWM2_B1IOPRU_ICSSG PWM Output BU14, Y18W13
PRG1_PWM2_B2IOPRU_ICSSG PWM Output BR16, W12V20, Y12
PRG1_PWM3_A0IOPRU_ICSSG PWM Output AY7V4
PRG1_PWM3_A1IOPRU_ICSSG PWM Output AAA7Y2
PRG1_PWM3_A2IOPRU_ICSSG PWM Output AV8Y5
PRG1_PWM3_B0IOPRU_ICSSG PWM Output BU8W5
PRG1_PWM3_B1IOPRU_ICSSG PWM Output BU13V13
PRG1_PWM3_B2IOPRU_ICSSG PWM Output BV13U14
PRG1_RGMII1_RXCIPRU_ICSSG RGMII Receive ClockAA7Y2
PRG1_RGMII1_RX_CTLIPRU_ICSSG RGMII Receive ControlY8AA5
PRG1_RGMII1_TXCIOPRU_ICSSG RGMII Transmit ClockV9W6
PRG1_RGMII1_TX_CTLOPRU_ICSSG RGMII Transmit ControlY9Y7
PRG1_RGMII2_RXCIPRU_ICSSG RGMII Receive ClockU11V10
PRG1_RGMII2_RX_CTLIPRU_ICSSG RGMII Receive ControlW12Y12
PRG1_RGMII2_TXCIOPRU_ICSSG RGMII Transmit ClockY10Y8
PRG1_RGMII2_TX_CTLOPRU_ICSSG RGMII Transmit ControlY11V9
PRG1_RGMII1_RD0IPRU_ICSSG RGMII Receive DataY7V4
PRG1_RGMII1_RD1IPRU_ICSSG RGMII Receive DataU8W5
PRG1_RGMII1_RD2IPRU_ICSSG RGMII Receive DataW8AA4
PRG1_RGMII1_RD3IPRU_ICSSG RGMII Receive DataV8Y5
PRG1_RGMII1_TD0OPRU_ICSSG RGMII Transmit DataAA8V5
PRG1_RGMII1_TD1OPRU_ICSSG RGMII Transmit DataU9W2
PRG1_RGMII1_TD2OPRU_ICSSG RGMII Transmit DataW9V6
PRG1_RGMII1_TD3OPRU_ICSSG RGMII Transmit DataAA9AA7
PRG1_RGMII2_RD0IPRU_ICSSG RGMII Receive DataW11AA10
PRG1_RGMII2_RD1IPRU_ICSSG RGMII Receive DataV11Y10
PRG1_RGMII2_RD2IPRU_ICSSG RGMII Receive DataAA12Y11
PRG1_RGMII2_RD3IPRU_ICSSG RGMII Receive DataY12V12
PRG1_RGMII2_TD0OPRU_ICSSG RGMII Transmit DataAA10Y6
PRG1_RGMII2_TD1OPRU_ICSSG RGMII Transmit DataV10AA8
PRG1_RGMII2_TD2OPRU_ICSSG RGMII Transmit DataU10Y9
PRG1_RGMII2_TD3OPRU_ICSSG RGMII Transmit DataAA11W9
PRG1_UART0_CTSnIPRU-ICSSG UART Clear to Send (active low)U15W16
PRG1_UART0_RTSnOPRU-ICSSG UART Request to Send (active low)U14W13
PRG1_UART0_RXDIPRU-ICSSG UART Receive DataV14Y16
PRG1_UART0_TXDOPRU-ICSSG UART Transmit DataW14U13