SPRSP65B April   2021  – July 2021 AM2431 , AM2432 , AM2434

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
    1. 3.1 Functional Block Diagram
  4. Revision History
  5. Device Comparison
    1. 5.1 Related Products
  6. Terminal Configuration and Functions
    1. 6.1 Pin Diagram
      1. 6.1.1 AM243x ALV Pin Diagram
      2. 6.1.2 AM243x ALX Pin Diagram
    2. 6.2 Pin Attributes (ALV Package)
    3. 6.3 Pin Attributes (ALX Package)
    4. 6.4 Signal Descriptions
      1. 6.4.1  ADC
        1.       MAIN Domain Instances
        2. 6.4.1.1 ADC0 Signal Descriptions
      2. 6.4.2  DDRSS
        1.       MAIN Domain Instances
        2. 6.4.2.1 DDRSS0 Signal Descriptions
      3. 6.4.3  GPIO
        1.       MAIN Domain Instances
        2. 6.4.3.1 GPIO0 Signal Descriptions
        3. 6.4.3.2 GPIO1 Signal Descriptions
        4.       MCU Domain Instances
        5. 6.4.3.3 MCU_GPIO0 Signal Descriptions
      4. 6.4.4  I2C
        1.       MAIN Domain Instances
        2. 6.4.4.1 I2C0 Signal Descriptions
        3. 6.4.4.2 I2C1 Signal Descriptions
        4. 6.4.4.3 I2C2 Signal Descriptions
        5. 6.4.4.4 I2C3 Signal Descriptions
        6.       MCU Domain Instances
        7. 6.4.4.5 MCU_I2C0 Signal Descriptions
        8. 6.4.4.6 MCU_I2C1 Signal Descriptions
      5. 6.4.5  MCAN
        1.       MAIN Domain Instances
        2. 6.4.5.1 MCAN0 Signal Descriptions
        3. 6.4.5.2 MCAN1 Signal Descriptions
      6. 6.4.6  SPI (MCSPI)
        1.       MAIN Domain Instances
        2. 6.4.6.1 MCSPI0 Signal Descriptions
        3. 6.4.6.2 MCSPI1 Signal Descriptions
        4. 6.4.6.3 MCSPI2 Signal Descriptions
        5. 6.4.6.4 MCSPI3 Signal Descriptions
        6. 6.4.6.5 MCSPI4 Signal Descriptions
        7.       MCU Domain Instances
        8. 6.4.6.6 MCU_MCSPI0 Signal Descriptions
        9. 6.4.6.7 MCU_MCSPI1 Signal Descriptions
      7. 6.4.7  UART
        1.       MAIN Domain Instances
        2. 6.4.7.1 UART0 Signal Descriptions
        3. 6.4.7.2 UART1 Signal Descriptions
        4. 6.4.7.3 UART2 Signal Descriptions
        5. 6.4.7.4 UART3 Signal Descriptions
        6. 6.4.7.5 UART4 Signal Descriptions
        7. 6.4.7.6 UART5 Signal Descriptions
        8. 6.4.7.7 UART6 Signal Descriptions
        9.       MCU Domain Instances
        10. 6.4.7.8 MCU_UART0 Signal Descriptions
        11. 6.4.7.9 MCU_UART1 Signal Descriptions
      8. 6.4.8  MDIO
        1.       MAIN Domain Instances
        2. 6.4.8.1 MDIO0 Signal Descriptions
      9. 6.4.9  CPSW
        1.       MAIN Domain Instances
        2. 6.4.9.1 CPSW3G0 Signal Descriptions
      10. 6.4.10 ECAP
        1.       MAIN Domain Instances
        2. 6.4.10.1 ECAP0 Signal Descriptions
        3. 6.4.10.2 ECAP1 Signal Descriptions
        4. 6.4.10.3 ECAP2 Signal Descriptions
      11.      EQEP
        1.       MAIN Domain Instances
        2. 6.4.11.1 EQEP0 Signal Descriptions
        3. 6.4.11.2 EQEP1 Signal Descriptions
        4. 6.4.11.3 EQEP2 Signal Descriptions
      12. 6.4.11 EPWM
        1.       MAIN Domain Instances
        2. 6.4.11.1  EPWM Signal Descriptions
        3. 6.4.11.2  EPWM0 Signal Descriptions
        4. 6.4.11.3  EPWM1 Signal Descriptions
        5. 6.4.11.4  EPWM2 Signal Descriptions
        6. 6.4.11.5  EPWM3 Signal Descriptions
        7. 6.4.11.6  EPWM4 Signal Descriptions
        8. 6.4.11.7  EPWM5 Signal Descriptions
        9. 6.4.11.8  EPWM6 Signal Descriptions
        10. 6.4.11.9  EPWM7 Signal Descriptions
        11. 6.4.11.10 EPWM8 Signal Descriptions
      13. 6.4.12 SERDES
        1.       MAIN Domain Instances
        2. 6.4.12.1 SERDES0 Signal Descriptions
      14. 6.4.13 USB
        1.       MAIN Domain Instances
        2. 6.4.13.1 USB0 Signal Descriptions
      15. 6.4.14 OSPI
        1.       MAIN Domain Instances
        2. 6.4.14.1 OSPI0 Signal Descriptions
      16. 6.4.15 GPMC
        1.       MAIN Domain Instances
        2. 6.4.15.1 GPMC0 Signal Descriptions
      17. 6.4.16 MMC
        1.       MAIN Domain Instances
        2. 6.4.16.1 MMC0 Signal Descriptions
        3. 6.4.16.2 MMC1 Signal Descriptions
      18. 6.4.17 FSITX
        1.       MAIN Domain Instances
        2. 6.4.17.1 FSI0 TX Signal Descriptions
        3. 6.4.17.2 FSI1 TX Signal Descriptions
      19. 6.4.18 FSIRX
        1.       MAIN Domain Instances
        2. 6.4.18.1 FSI0 RX Signal Descriptions
        3. 6.4.18.2 FSI1 RX Signal Descriptions
        4. 6.4.18.3 FSI2 RX Signal Descriptions
        5. 6.4.18.4 FSI3 RX Signal Descriptions
        6. 6.4.18.5 FSI4 RX Signal Descriptions
        7. 6.4.18.6 FSI5 RX Signal Descriptions
      20. 6.4.19 CPTS
        1.       MAIN Domain Instances
        2. 6.4.19.1 CPTS0 Signal Descriptions
        3. 6.4.19.2 CP GEMAC CPTS0 Signal Descriptions
      21. 6.4.20 ICSSG
        1.       MAIN Domain Instances
        2. 6.4.20.1 PRU_ICSSG0 Signal Descriptions
        3. 6.4.20.2 PRU_ICSSG1 Signal Descriptions
      22. 6.4.21 DMTIMER
        1.       MAIN Domain Instances
        2. 6.4.21.1 DMTIMER Signal Descriptions
        3.       MCU Domain Instances
        4. 6.4.21.2 MCU_DMTIMER Signal Descriptions
      23. 6.4.22 TRACE
        1.       MAIN Domain Instances
        2. 6.4.22.1 Trace Signal Descriptions
      24. 6.4.23 JTAG
        1.       MAIN Domain Instances
        2. 6.4.23.1 JTAG Signal Descriptions
      25. 6.4.24 SYSBOOT
        1.       MAIN Domain Instances
        2. 6.4.24.1 Sysboot Signal Descriptions
      26. 6.4.25 SYSTEM
        1.       MAIN Domain Instances
        2. 6.4.25.1 System Signal Descriptions
        3.       MCU Domain Instances
        4. 6.4.25.2 MCU System Signal Descriptions
      27. 6.4.26 CLOCK
        1.       MCU Domain Instances
        2. 6.4.26.1 MCU Clock Signal Descriptions
      28. 6.4.27 VMON
        1. 6.4.27.1 VMON Signal Description
      29. 6.4.28 Power Supply
        1. 6.4.28.1 Power Supply Signal Description
    5. 6.5 Pin Multiplexing
    6. 6.6 Connections for Unused Pins
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Operating Performance Points
    6. 7.6  Power Consumption Summary
    7. 7.7  Electrical Characteristics
      1. 7.7.1 Fail-Safe Reset (FS RESET) Electrical Characteristics
      2. 7.7.2 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      3. 7.7.3 High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 7.7.4 eMMCPHY Electrical Characteristics
      5. 7.7.5 SDIO Electrical Characteristics
      6. 7.7.6 ADC12B Electrical Characteristics
      7. 7.7.7 LVCMOS Electrical Characteristics
      8. 7.7.8 USB2PHY Electrical Characteristics
      9. 7.7.9 DDR Electrical Characteristics
    8. 7.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.8.2 Hardware Requirements
      3. 7.8.3 Programming Sequence
      4. 7.8.4 Impact to Your Hardware Warranty
    9. 7.9  Thermal Resistance Characteristics
      1. 7.9.1 Thermal Resistance Characteristics
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Sequencing
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Power-Up Sequencing
        3. 7.10.2.3 Power-Down Sequencing
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Safety Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input Clocks / Oscillators
          1. 7.10.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
      5. 7.10.5 Peripherals
        1. 7.10.5.1  CPSW3G
          1. 7.10.5.1.1 CPSW3G MDIO Timing
          2. 7.10.5.1.2 CPSW3G RMII Timing
          3. 7.10.5.1.3 CPSW3G RGMII Timing
        2. 7.10.5.2  DDRSS
        3. 7.10.5.3  ECAP
        4. 7.10.5.4  EPWM
        5. 7.10.5.5  EQEP
        6. 7.10.5.6  FSI
        7. 7.10.5.7  GPIO
        8. 7.10.5.8  GPMC
          1. 7.10.5.8.1 GPMC and NOR Flash — Synchronous Mode
          2. 7.10.5.8.2 GPMC and NOR Flash — Asynchronous Mode
          3. 7.10.5.8.3 GPMC and NAND Flash — Asynchronous Mode
        9. 7.10.5.9  I2C
          1. 7.10.5.9.1 Timing Requirements for I2C Input Timings
        10. 7.10.5.10 MCAN
        11. 7.10.5.11 MCSPI
          1. 7.10.5.11.1 MCSPI — Master Mode
          2. 7.10.5.11.2 MCSPI — Slave Mode
        12. 7.10.5.12 MMCSD
          1. 7.10.5.12.1 MMC0 - eMMC Interface
            1. 7.10.5.12.1.1 Legacy SDR Mode
            2. 7.10.5.12.1.2 High Speed SDR Mode
            3. 7.10.5.12.1.3 High Speed DDR Mode
            4. 7.10.5.12.1.4 HS200 Mode
          2. 7.10.5.12.2 MMC1 - SD/SDIO Interface
            1. 7.10.5.12.2.1 Default Speed Mode
            2. 7.10.5.12.2.2 High Speed Mode
            3. 7.10.5.12.2.3 UHS–I SDR12 Mode
            4. 7.10.5.12.2.4 UHS–I SDR25 Mode
            5. 7.10.5.12.2.5 UHS–I SDR50 Mode
            6. 7.10.5.12.2.6 UHS–I DDR50 Mode
            7. 7.10.5.12.2.7 UHS–I SDR104 Mode
        13. 7.10.5.13 CPTS
        14. 7.10.5.14 OSPI
          1. 7.10.5.14.1 OSPI With Data Training
            1. 7.10.5.14.1.1 OSPI Switching Characteristics – Data Training
          2. 7.10.5.14.2 OSPI Without Data Training
            1. 7.10.5.14.2.1 OSPI SDR Timing
            2. 7.10.5.14.2.2 OSPI DDR Timing
        15. 7.10.5.15 PCIe
        16. 7.10.5.16 PRU_ICSSG
          1. 7.10.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)
            1. 7.10.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing
            2. 7.10.5.16.1.2 PRU_ICSSG PRU Parallel Capture Mode Timing
            3. 7.10.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing
            4. 7.10.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface
              1. 7.10.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing
          2. 7.10.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 7.10.5.16.2.1 PRU_ICSSG PWM Timing
          3. 7.10.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)
            1. 7.10.5.16.3.1 PRU_ICSSG IEP Timing
          4. 7.10.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)
            1. 7.10.5.16.4.1 PRU_ICSSG UART Timing
          5. 7.10.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)
            1. 7.10.5.16.5.1 PRU_ICSSG ECAP Timing
          6. 7.10.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 7.10.5.16.6.1 PRU_ICSSG MDIO Timing
            2. 7.10.5.16.6.2 PRU_ICSSG MII Timing
            3. 7.10.5.16.6.3 PRU_ICSSG RGMII Timing
        17. 7.10.5.17 Timers
        18. 7.10.5.18 UART
        19. 7.10.5.19 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Trace
        2. 7.10.6.2 JTAG
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-R5F Subsystem (R5FSS)
      2. 8.2.2 Arm Cortex-M4F (M4FSS)
    3. 8.3 Accelerators and Coprocessors
      1. 8.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)
    4. 8.4 Other Subsystems
      1. 8.4.1 PDMA Controller
      2. 8.4.2 Peripherals
        1. 8.4.2.1  ADC
        2. 8.4.2.2  DCC
        3. 8.4.2.3  Dual Date Rate (DDR) External Memory Interface (DDRSS)
        4. 8.4.2.4  ECAP
        5. 8.4.2.5  EPWM
        6. 8.4.2.6  ELM
        7. 8.4.2.7  ESM
        8. 8.4.2.8  GPIO
        9. 8.4.2.9  EQEP
        10. 8.4.2.10 GPMC
        11. 8.4.2.11 I2C
        12. 8.4.2.12 MCAN
        13. 8.4.2.13 MCRC Controller
        14. 8.4.2.14 MCSPI
        15. 8.4.2.15 MMCSD
        16. 8.4.2.16 OSPI
        17. 8.4.2.17 Peripheral Component Interconnect Express (PCIe)
        18. 8.4.2.18 Serializer/Deserializer (SerDes)
        19. 8.4.2.19 RTI
        20. 8.4.2.20 DMTIMER
        21. 8.4.2.21 UART
        22. 8.4.2.22 Universal Serial Bus Subsystem(USBSS)
  9. Applications, Implementation, and Layout
    1. 9.1 Power Supply Mapping
    2. 9.2 Device Connection and Layout Fundamentals
      1. 9.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.2.1.1 Power Distribution Network Implementation Guidance
      2. 9.2.2 External Oscillator
      3. 9.2.3 JTAG and EMU
      4. 9.2.4 Unused Pins
    3. 9.3 Peripheral- and Interface-Specific Design Information
      1. 9.3.1 General Routing Guidelines
      2. 9.3.2 DDR Board Design and Layout Guidelines
      3. 9.3.3 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.3.3.1 No Loopback and Internal Pad Loopback
        2. 9.3.3.2 External Board Loopback
        3. 9.3.3.3 DQS (only available in Octal Flash devices)
      4. 9.3.4 USB VBUS Design Guidelines
      5. 9.3.5 System Power Supply Monitor Design Guidelines
      6. 9.3.6 High Speed Differential Signal Routing Guidance
      7. 9.3.7 Thermal Solution Guidance
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALV|441
  • ALX|293
Thermal pad, mechanical data (Package|Pins)
Orderable Information
GPMC and NOR Flash — Synchronous Mode

Table 7-50 and Table 7-51 present timing requirements and switching characteristics for GPMC and NOR Flash - Synchronous Mode.

Table 7-50 GPMC and NOR Flash Timing Requirements — Synchronous Mode see Figure 7-37, Figure 7-38, and Figure 7-41
NO. PARAMETER DESCRIPTION MODE(4) MIN MAX MIN MAX UNIT
GPMC_FCLK = 100 MHz(1) GPMC_FCLK = 133 MHz(1)
F12 tsu(dV-clkH) Setup time, input data GPMC_AD[15:0] valid before output clock GPMC_CLK high div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
1.81 1.11 ns
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
1.06 3.50 ns
F13 th(clkH-dV) Hold time, input data GPMC_AD[15:0] valid after output clock GPMC_CLK high div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.28 2.28 ns
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.28 2.28 ns
F21 tsu(waitV-clkH) Setup time, input wait GPMC_WAIT[j](2)(3) valid before output clock GPMC_CLK high div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
1.81 1.11 ns
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
1.06 3.50 ns
F22 th(clkH-waitV) Hold time, input wait GPMC_WAIT[j](2)(3) valid after output clock GPMC_CLK high div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.28 2.28 ns
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.8 2.28 ns
GPMC_FCLK select
  • gpmc_fclk_sel[1:0] = 2b01 to select the 100MHz GPMC_FCLK
  • gpmc_fclk_sel[1:0] = 2b00 to select the 133MHz GPMC_FCLK
In GPMC_WAIT[j], j is equal to 0 or 1.
Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-Purpose Memory Controller (GPMC) section in the device TRM.
For div_by_1_mode:
  • GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
    • GPMC_CLK frequency = GPMC_FCLK frequency

For not_div_by_1_mode:
  • GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:
    • GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)

For GPMC_FCLK_MUX:
  • CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz

For TIMEPARAGRANULARITY_X1:
  • GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)
Table 7-51 GPMC and NOR Flash Switching Characteristics – Synchronous Mode see Figure 7-37, Figure 7-38, Figure 7-39, Figure 7-40, and Figure 7-41
NO.(2) PARAMETER DESCRIPTION MODE(17) MIN MAX MIN MAX UNIT
100 MHz 133 MHz
F0 1 / tc(clk) Period, output clock GPMC_CLK(15) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
10.00 7.52 ns
F1 tw(clkH) Typical pulse duration, output clock GPMC_CLK high div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
0.475P - 0.3(14) 0.475P - 0.3(14) ns
F1 tw(clkL) Typical pulse duration, output clock GPMC_CLK low div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
0.475P - 0.3(14) 0.475P - 0.3(14) ns
tdc(clk) Duty cycle error, output clock GPMC_CLK div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-500.00 500.00 -500.00 500.00 ps
tJ(clk) Jitter standard deviation, output clock GPMC_CLK(16) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
33.33 33.33 ps
tR(clk) Rise time, output clock GPMC_CLK div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.0 2.0 ns
tF(clk) Fall time, output clock GPMC_CLK div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.0 2.0 ns
tR(do) Rise time, output data GPMC_AD[15:0] div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.0 2.0 ns
tF(do) Fall time, output data GPMC_AD[15:0] div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.0 2.0 ns
F2 td(clkH-csnV) Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] transition(13) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
F - 2.2 (5) F + 3.75 F - 2.2 (5) F + 3.75 ns
F3 td(clkH-CSn[i]V) Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] invalid(13) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
E - 2.2 (4) E + 1.31 E - 2.2 (4) E + 4.5 ns
F4 td(aV-clk) Delay time, output address GPMC_A[27:1] valid to output clock GPMC_CLK first edge div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
B - 2.3 (2) B + 4.5 B - 2.3 (2) B + 4.5 ns
F5 td(clkH-aIV) Delay time, output clock GPMC_CLK rising edge to output address GPMC_A[27:1] invalid div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3 4.5 -2.3 4.5 ns
F6 td(be[x]nV-clk) Delay time, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n valid to output clock GPMC_CLK first edge div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
B - 2.3 (2) B + 1.9 B - 2.3 (2) B + 1.9 ns
F7 td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n invalid(10) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
D - 2.3(3) D + 1.9 D - 2.3 (3) D + 1.9 ns
F7 td(clkL-be[x]nIV) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(11) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
D - 2.3 (3) D + 1.9 D - 2.3 (3) D + 1.9 ns
F7 td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(12) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
D - 2.3 (3) D + 1.9 D - 2.3 (3) D + 1.9 ns
F8 td(clkH-advn) Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE transition div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
G - 2.3(6) G + 4.5 G - 2.3 (6) G + 4.5 ns
F9 td(clkH-advnIV) Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE invalid div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
D - 2.3 (3) D + 4.5 D - 2.3 (3) D + 4.5 ns
F10 td(clkH-oen) Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn transition div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.3H (7) H + 3.5 H - 2.3 (7) H + 3.5 ns
F11 td(clkH-oenIV) Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn invalid div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
E - 2.3 (7) E + 3.5 E - 2.3 (7) E + 3.5 ns
F14 td(clkH-wen) Delay time, output clock GPMC_CLK rising edge to output write enable GPMC_WEn transition div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
I - 2.3 (8) I + 4.5 I - 2.3 (8) I + 4.5 ns
F15 td(clkH-do) Delay time, output clock GPMC_CLK rising edge to output data GPMC_AD[15:0] transition(10) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 (9) J + 2.7 J - 2.3 (9) J + 2.7 ns
F15 td(clkL-do) Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(11) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 (9) J + 2.7 J - 2.3 (9) J + 2.7 ns
F15 td(clkL-do). Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(12) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 (9) J + 2.7 J - 2.3 (9) J + 2.7 ns
F17 td(clkH-be[x]n) Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE transition(10) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 (9) J + 1.9 J - 2.3 (9) J + 1.9 ns
F17 td(clkL-be[x]n) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(11) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 (9) J + 1.9 J - 2.3 (9) J + 1.9 ns
F17 td(clkL-be[x]n). Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(12) div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 (9) J + 1.9 J - 2.3 (9) J + 1.9 ns
F18 tw(csnV) Pulse duration, output chip select GPMC_CSn[i](13) low Read A A ns
Write A A ns
F19 tw(be[x]nV) Pulse duration, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n low Read C C ns
Write C C ns
F20 tw(advnV) Pulse duration, output address valid and address latch enable GPMC_ADVn_ALE low Read K K ns
Write K K ns
B = ClkActivationTime × GPMC_FCLK(14)
For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For csn falling edge (CS activated):
  • Case GPMCFCLKDIVIDER = 0:
    • F = 0.5 × CSExtraDelay × GPMC_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • F = 0.5 × CSExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
    • F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • F = 0.5 × CSExtraDelay × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime) is a multiple of 3)
    • F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
    • F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
For ADV falling edge (ADV activated):
  • Case GPMCFCLKDIVIDER = 0:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
    • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Reading mode:
  • Case GPMCFCLKDIVIDER = 0:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
    • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Writing mode:
  • Case GPMCFCLKDIVIDER = 0:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
    • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):
  • Case GPMCFCLKDIVIDER = 0:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime) is a multiple of 3)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
    • H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)

For OE rising edge (OE deactivated):
  • Case GPMCFCLKDIVIDER = 0:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime) is a multiple of 3)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
    • H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
For WE falling edge (WE activated):
  • Case GPMCFCLKDIVIDER = 0:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime) is a multiple of 3)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
    • I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)

For WE rising edge (WE deactivated):
  • Case GPMCFCLKDIVIDER = 0:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK (14)
  • Case GPMCFCLKDIVIDER = 1:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime) is a multiple of 3)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
    • I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
J = GPMC_FCLK(14)
First transfer only for CLK DIV 1 mode.
Half cycle; for all data after initial transfer for CLK DIV 1 mode.
Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
P = GPMC_CLK period in ns
Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.
The jitter probability density can be approximated by a Gaussian function.
For div_by_1_mode:
  • GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:
    • GPMC_CLK frequency = GPMC_FCLK frequency

For GPMC_FCLK_MUX:
  • CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz

For TIMEPARAGRANULARITY_X1:
  • GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)

For no extra_delay:
  • GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed
  • GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed
  • GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed
  • GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed
GUID-15E6DF0F-CED7-41F6-9B7C-2CB448FFBD55-low.gif
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-37 GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0)
GUID-BF774493-D226-4746-84E1-EC253E2F6E02-low.gif
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-38 GPMC and NOR Flash — Synchronous Burst Read — 4x16–bit (GPMCFCLKDIVIDER = 0)
GUID-303303DA-BB3E-4C9A-90F8-0578C57AA6AD-low.gif
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-39 GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)
GUID-7E193CA0-1BFB-4848-BF90-F82174643C4A-low.gif
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-40 GPMC and Multiplexed NOR Flash — Synchronous Burst Read
GUID-D3F03E5A-08AB-4266-B4A5-94F63115813E-low.gif
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-41 GPMC and Multiplexed NOR Flash — Synchronous Burst Write