SPRSP65F April 2021 – January 2023 AM2431 , AM2432 , AM2434
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
OSPI0 offers two data capture modes, PHY mode and Tap mode.
PHY mode uses an internal reference clock to transmit and receive data via a DLL based PHY, where each reference clock cycle produces a single cycle of OSPI0_CLK for Single Data Rate (SDR) transfers or a half cycle of OSPI0_CLK for Double Data Rate (DDR) transfers. PHY mode supports four clocking topologies for the receive data capture clock. Internal PHY Loopback - uses the internal reference clock as the PHY receive data capture clock. Internal Pad Loopback - uses OSPI0_LBCLKO looped back into the PHY from the OSPI0_LBCLKO pin as the PHY receive data capture clock. External Board Loopback - uses OSPI0_LBCLKO looped back into the PHY from the OSPI0_DQS pin as the PHY receive data capture clock. DQS - uses the DQS output from the attached device as the PHY receive data capture clock. SDR transfers are not supported when using the Internal Pad Loopback and DQS clocking topologies. DDR transfers are not supported when using the Internal PHY Loopback or Internal Pad Loopback clocking topologies.
Tap mode uses an internal reference clock with selectable taps to adjusted data transmit and receive capture delays relative to OSPI0_CLK, which is a divide by 4 of the internal reference clock for SDR transfers or a divide by 8 of the internal reference clock for DDR transfers. Tap mode only supports one clocking topology for the receive data capture clock. No Loopback - uses the internal reference clock as the Tap receive data capture clock. This clocking topology supports a maximum internal reference clock rate of 200 MHz, which produces an OSPI0_CLK rate up to 50 MHz for SDR mode or 25 MHz for DDR mode.
For more details about features and additional description information on the device Octal Serial Peripheral Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
Section 7.10.5.14.1 defines timing requirements and switching characteristics associated with PHY mode and Section 7.10.5.14.2 defines timing requirements and switching characteristics associated with Tap mode.
Table 7-93 presents timing conditions for OSPI0.
| PARAMETER | MODE | MIN | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| INPUT CONDITIONS | ||||||
| SRI | Input slew rate | 1 | 6 | V/ns | ||
| OUTPUT CONDITIONS | ||||||
| CL | Output load capacitance | 3 | 10 | pF | ||
| PCB CONNECTIVITY REQUIREMENTS | ||||||
| td(Trace Delay) | Propagation delay of OSPI0_CLK trace | No Loopback Internal PHY Loopback Internal Pad Loopback |
450 | ps | ||
| Propagation delay of OSPI0_LBCLKO trace | External Board Loopback | 2L(1) - 30 | 2L(1) + 30 | ps | ||
| Propagation delay of OSPI0_DQS trace | DQS | L(1) - 30 | L(1) + 30 | ps | ||
| td(Trace Mismatch Delay) | Propagation delay mismatch of OSPI0_D[7:0] and OSPI0_CSn[3:0] relative to OSPI0_CLK | All modes | 60 | ps | ||
For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device TRM.