Refer to the PDF data sheet for device specific package drawings
Power is supplied to the Phase-Locked Loop circuits (PLLs) by internal regulators that derive their power from off-chip power-sources.
There is one PLL in the MCU domain:
There are six PLLs in the MAIN domain:
For more information, see:
The input reference clock (MCU_OSC0_XI / MCU_OSC0_XO) is specified and the lock time is ensured by the PLL controller, as documented in the Device Configuration chapter in the device TRM.