The TCAN284x-Q1 is a family of system basis chips (SBC) that integrate the CAN FD transceiver. The CAN FD transceiver supports data rates up to 8Mbps while meeting the high-speed CAN physical layer standards: ISO 11898-2:2024. The TCAN2847x-Q1 integrate a LIN transceiver that supports data rates up to 200kbps when slope control is disabled and programmed for fast mode. The LIN transceiver physical layer transceiver is compliant to LIN 2.2A and ISO/DIS 17987–4 and SAE J2602 standards. These data rates support end of line programming. The TCAN2845x-Q1 and TCAN2847x-Q1 supports selective wake up on dedicated CAN-frames. The device can also wake up using remote wake up using CAN bus implementing the ISO 11898-2:2024 Wake Up Pattern (WUP). The TCAN284x-Q1 supports 3.3V and 5V processors based upon VCC1 voltage. The device has a Serial Peripheral Interface (SPI) that connects to a local microprocessor for configuration. The TCAN284x-Q1 provide a software development pin to help implementer with development. In this mode, the watchdog is still active but only sets a flag.

The TCAN284x3 variant of the devices provide a VCC1 of 3.3V output and the TCAN284x5 variant of the device provides a VCC1 of 5V output. These devices have a separate 5V LDO, VCC2. The ability to control an external PNP power transistor is provided to support output voltages of 1.8V, 2.5V, 3.3V or 5V at the VEXCC pin. VCC2 and VEXCC are short to battery protected. A 5V input supply is needed at the VCAN pin for the CAN FD transceiver.

The CAN bus has two logical states during operation: recessive and dominant. See Figure 7-1 and Figure 7-2.

Recessive bus state is when the bus is biased to a common mode of about 2.5V through the high resistance internal input resistors of the receiver of each node on the bus across the termination resistors. Recessive is equivalent to logic high and is typically a differential voltage on the bus of almost 0V. Recessive state is also the idle state.

Dominant bus state is when the bus is driven differentially by one or more drivers. Current is induced to flow through the termination resistors and generate a differential voltage on the bus. Dominant is equivalent to logic low and is a differential voltage on the bus greater than the minimum threshold for a CAN dominant. A dominant state overwrites the recessive state.

During arbitration, multiple CAN nodes can transmit a dominant bit at the same time. The differential voltage of the bus is greater than the differential voltage of a single driver.

Transceivers with low power Standby Mode have a third bus state where the bus terminals are weakly biased to ground using the high resistance internal resistors of the receiver. See Figure 7-1 and Figure 7-2.