SLLSFE8 Data sheet

SLLSFE8B November 2024 – November 2025 TCAN2845-Q1 , TCAN2847-Q1

PRODUCTION DATA

8.3.6 CAN FD Transceiver

Figure 8-9 shows the block diagram for the CAN FD Transceiver.

The CTXD is the input to the CAN FD transmitter from the processor that controls the state of the CAN FD bus. When CTXD is low, the bus output is dominant. When CTXD is high, the bus output is recessive which is a logic 0. The CTXD input structure is compatible with processors with 3.3V to 5V V_O. CTXD has an internal pullup resistor to VCC1. The bus is protected from being stuck dominant through a system failure driving CTXD low through the dominant state time-out timer.

CRXD is the output of the CAN FD receiver. When a CAN wake event takes place the CRXD pin is latched low. CRXD also indicates the local wake up (LWU) from the high voltage WAKE pins. The CRXD is a push-pull output buffer and as such an external pull-up is not needed. In restart mode, the RXD pins are driven high. When VCC1 is > UVCC1 for t_{RSTN_act}, the device automatically transition to standby mode. The CRXD pin is then pulled low to indicate a wake up request. The CRXD pin can be programmed to toggle low/high with a pulse width of t_TOGGLE, see Section 8.4.7.3.1 as an example of this feature.

The VCAN pin is the 5V supply input for the CAN FD transceiver. VCAN is monitored for under-voltage events, UVCAN. When VCAN is present and not in a fault state, register 8'h4F[1], VCAN_STATUS, is set to 1b. For the CAN FD transceiver to be available, VCAN must be present. This pin is also used for EEPROM writing so must be on for this function to happen.

The CAN FD transceiver can be separately programmed outside of the SBC mode control or tied to the SBC mode control. When tied to the SBC mode control, changing the SBC mode to normal mode automatically changes the transceiver to ON and transceiver is wake capable in all other modes. When programmed separately than the SBC modes, there are certain states that the transceivers cannot be in for the mode.

TCAN2845-Q1 TCAN2847-Q1 CAN Transceiver Block
Diagram

Figure 8-9 CAN Transceiver Block Diagram

Note: If a mode change is initiated and the transceiver is not in an allowed state, the mode change does not take place. The MODE_ERR interrupt at 8'h5A[3] is set to 1b.

This includes changing the transceiver configuration to a disallowed state while in the current SBC mode. See Table 8-1 and Table 8-1 for allowed transceiver configurations for each SBC mode. Here are a few specific cases for consideration:

A transceiver in Normal mode configured for listen, wake capable and off can transition to standby mode and the state are the same.
Transitioning to restart mode is wake capable unless the transceiver is programmed off.
Transitioning from restart mode to standby mode is wake capable unless the transceiver is programmed off.
When using the SWE timer and the timer times out, the transceivers automatically becomes wake capable when entering sleep mode or fail-safe mode.

Note: If the device is in SBC normal mode and the transceivers are programmed on, the TXD pin is checked. If the TXD pin is dominant, the transceiver does not turn on the transmitter until the TXD pin has transitioned to recessive.

The CAN FD transceiver supports off, on, listen and wake capable. The state of the transceiver is programmed using register 8'h10[2:0]. On represents what is normal mode for a stand-alone transceiver. The CAN transceiver defaults to wake capable when entering fail-safe mode but can be disabled for this mode by using CAN1_FSM_DIS at register 8'h10[3] = 1b.

Table 8-1 CAN FD Transceiver Programmable State by SBC Mode

SBC Mode	On	Listen	Wake Capable	Off	SBC Mode Control
Normal	✓	✓	✓	✓	On
Standby		✓	✓	✓	Wake Capable
Sleep			✓ default	✓	Wake Capable
Restart			✓ default	✓	Wake Capable
Fail-safe			✓ default	✓	Wake Capable

Note:

When entering SBC restart mode, the transceiver changes wake capable
When entering SBC fail-safe mode, the transceiver defaults to wake capable.