SLLSFE8 Data sheet

SLLSFE8B November 2024 – November 2025 TCAN2845-Q1 , TCAN2847-Q1

PRODUCTION DATA

6.8 Timing Requirements

Over recommended operating range (unless otherwise noted)

Parameter		Test Condition	MIN	NOM	MAX	UNIT
SUPPLY
t_PWRUP	Time after VSUP exceedsUVSUPand VCC1> UVCC1 ⁽⁵⁾	Device powers up enters restart			3.5	ms
t_VCCSS	Softstart time for VCC1, VCC2 and VEXCC ⁽⁵⁾	Time required for VCC1, VCC2 and VEXCC to ramp from 0V to 90% of regulated value		0.75	1.25	ms
t_UVFLTR	Under-voltage detection filter time for VCC1, VCC2 and VEXCC ⁽⁵⁾		25		50	µs
t_UVCC1PR	Under-voltage filter time for VCC1 pre-warning ⁽⁵⁾		2		12	µs
t_UVCANFLTR	Under-voltage filter time for VCAN ⁽⁵⁾		2		10	µs
t_OVFLTR	Over-voltage detect filter time on VCC1, VCC2 and VEXCC ⁽⁵⁾		20		45	µs
t_OVFLTRVHSS	Over-voltage detect filter time on VHSS ⁽⁵⁾		4		12	µs
t_VSC	Short to ground on VCC1, VCC2 and VEXCC detection filter time ⁽⁵⁾		75	100	125	µs
t_VSCLS	Short to ground for VCC1 and VEXCC detection filter time when load sharing ⁽⁵⁾		75	100	125	µs
t_LDOON	Time LDO is on to determine if a fault event is present after a previous uncleared detection ⁽⁵⁾	See Figure 7-19			3.8	ms
t_LDOOFF	Time VCC1 LDO is off in fail-safe mode before accepting wake events and checking for fault conditions ⁽⁵⁾		250	300	350	ms
MODE CHANGE
t_{MODE_STBY_NOM_CTRX}	CAN transceiver state change time based upon SPI write from off or wake capable to on or listen state where CRXD mirror CAN bus ⁽⁵⁾				70	µs
t_{MODE_STBY_NOM_LTRX}	LIN transceiver state change time based upon SPI write from off or wake capable to on or fast state where LRXD mirror LIN bus ⁽⁵⁾				70	µs
t_{MODE_NOM_SLP}	Time from SPI sleep command where CAN and/or LIN transceiver is off and RXD does not reflect the bus ⁽⁵⁾	See Figure 7-20			200	µs
t_{MODE_NOM_STBY}	SPI write to go to standby from normal mode ⁽⁵⁾	See Figure 7-21			70	µs
DEVICE TIMING
t_{RSTN_act}	Reset delay after recovering from undervoltage (VCC1 ≥ UVCC1R to nRST release) ⁽⁵⁾	See Figure 7-18, Figure 7-19, Figure 8-29 and Figure 10-8 as examples	1.5	2	2.5	ms
t_NRSTIN	Input pulse required on the nRST pin to recognize a device reset ⁽⁵⁾	See Figure 8-44	75	100	125	µs
t_RSTTO	Restart timer. Timer starts when VCC1 < UVCC1F. The device enters fail-safe mode (if enabled) or Sleep mode (fail-safe mode disabled) when the timer expires before the UVCC1 recovery. ⁽⁵⁾	Measured from nRST active to LIMP active	120	150	180	ms
t_{NRST_TOG}	Reset pulse duration due to watchdog error ⁽⁵⁾	Register 8'h29[5] = 0, see Figure 8-25	1.5	2	2.5	ms
t_{NRST_TOG}	Reset pulse duration due to watchdog error ⁽⁵⁾	Register 8'h29[5] = 1, see Figure 8-25	10	15	20	ms
t_{nINT_TI}	nINT output pulse width (low) when nINT_TOG_EN is enabled. ⁽⁵⁾	Register 8'h1B[0] = 1b	75	100	125	µs
t_{nINT_TP}	nINT output pulse width (high) when nINT_TOG_EN is enabled ⁽⁵⁾	Register 8'h1B[0] = 1b	75	100	125	µs
t_{WK_TIMEOUT}	Bus wake-up timeout value	See Figure 8-29	0.8		2	ms
t_{WK_FILTER}	Bus time to meet filtered bus requirements for wake up request	See Figure 8-29	0.5		1.8	µs
t_{WK_WIDTH_MIN}	Minimum WAKE Pin pulse width⁽²⁾⁽³⁾⁽⁴⁾⁽⁵⁾ See Figure 8-34	Register 8'h11[3:2] = 00b	10			ms
		Register 8'h11[3:2] = 01b	20			ms
		Register 8'h11[3:2] = 10b	40			ms
		Register 8'h11[3:2] = 11b	80			ms
t_{WK_WIDTH_INVALID}	Maximum WAKE Pin pulse width that is considered invalid ⁽²⁾⁽³⁾⁽⁴⁾⁽⁵⁾ See Figure 8-34	Register 8'h11[3:2] = 00b			5	ms
		Register 8'h11[3:2] = 01b			10	ms
		Register 8'h11[3:2] = 10b			20	ms
		Register 8'h11[3:2] = 11b			40	ms
t_{WK_WIDTH_MAX}	Maximum WAKE Pin pulse window ⁽²⁾⁽³⁾⁽⁴⁾⁽⁵⁾ See Figure 8-34	Register 8'h11[1:0] = 00b	750		950	ms
		Register 8'h11[1:0] = 01b	1000		1250	ms
		Register 8'h11[1:0] = 10b	1500		1875	ms
		Register 8'h11[1:0] = 11b	2000		2500	ms
t_{WK_CYC}	Sampling window for cyclic sensing; Standby or Sleep mode. ⁽⁵⁾ see Figure 8-37	Register 8'h12[5] = 0b	10	25	35	µs
t_{WK_CYC}		Register 8'h12[5] = 1b	55	75	85	µs
t_{SILENCE_CAN}	Timeout for bus inactivity Timer is reset and restarted, when bus changes from dominant to recessive or inversely .⁽⁵⁾		0.6		1.2	s
t_INACTIVE	SWE timer used for fail-safe and mode inactivity	Can be programmed to different values using register 8'h1C[6:3]	4	5	6	min
t_Bias	Time from the start of a dominant-recessive-dominant sequence	Each phase 6µs until Vsym ≥ 0.1. See Figure 7-10			250	µs
t_SW	SW pin filter time for a state change to be recognized ⁽⁵⁾		130			µs
t_INITWD	Initial long window for watchdog ⁽⁵⁾ see Figure 8-62	WD_CONFIG_1 register 8'h13[1:0] = 00b	127	150	173	ms
		WD_CONFIG_1 register 8'h13[1:0] = 01b	255	300	345	ms
		WD_CONFIG_1 register 8'h13[1:0] = 10b (default)	510	600	690	ms
		WD_CONFIG_1 register 8'h13[1:0] = 11b	850	1000	1150	ms
f_PWM-ACC	HSS1-4 PWM Frequency accuracy⁽⁵⁾	HSS set to PWM and PWM frequency set to 200Hz or 400Hz per PWMx_FREQ bit	–10		10	%
t_WD-ACC	Timeout watchdog timing accuracy⁽⁵⁾	Timeout watchdog enabled. Typical values for watchdog timer selected per Table 8-16	–15	tWD	15	%
t_WD-ACC	Window and Q&A watchdog timing accuracy⁽⁵⁾	Window watchdog or Q&A watchdog enabled. Typical values for watchdog timer selected per Table 8-16	–10	tWD	10	%
t_TMR-ACC	Timer1, Timer2 period/on-time accuracy OR SWE timer accuracy⁽⁵⁾	Typical value of Timer1 or Timer2 configured per register 8'h25 (TIMER1_CONFIG) or 8'h26 (TIMER2_CONFIG); Typical value of SWE timer configured per 8'h25 (SWE_TIMER_SET)	–15		15	%
t_{CTXD_DTO}	CAN TXD dominant time out⁽¹⁾⁽⁵⁾	R_L = 60Ω, C_L = open; See Figure 7-7	1		5	ms
t_{LTXD_DTO}	LIN TXD dominant time out⁽⁵⁾		20	45	80	ms
t_TOGGLE	RXD pin toggle timing when programmed after a WUP ⁽⁵⁾	See Figure 8-29	5	10	15	µs
F_OSC-16M	16MHz clock frequency		15.36	16	16.64	MHz
F_OSC-1M	1MHz clock frequency		0.94	1.04	1.14	MHz
F_OSC-10k	10kHz clock frequency		8.8	10.4	12	kHz

(1) The CTXD dominant time out (t_{CTXD_DTO}) disables the driver of the transceiver once the CTXD has been dominant longer than t_{CTXD_DTO}, which releases the CAN bus lines to recessive, preventing a local failure from locking the bus dominant. The driver can only transmit dominant again after CTXD has been returned HIGH (recessive). The dominant timeout feature protects the CAN bus from locking the bus dominant but limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on CTXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the t_{CTXD_DTO} minimum, limits the minimum bit rate. The minimum bit rate can be calculated by:

Equation 1.

M i n i m u m B i t R a t e = \frac{11}{t_{C T X D_D T O}} = \frac{11 b i t s}{1.2 m s} = 9.2 k b p s

(2) This parameter is valid only when register 11h[7:6] = 11b

(3) This is the minimum pulse width for a WAKE pin input that device detects as a good pulse. Value between the minimum t_{WK_WIDTH_MIN} and maximum t_{WK_WIDTH_INVALID}is indeterminate and is sometimes but not always considered valid.

(4) This parameter is set based upon the programmed value for t_{WK_WIDTH_INVALID} register 11h[3:2]

(5) Specified by design and characterization