SLLSFE8B November   2024  – November 2025 TCAN2845-Q1 , TCAN2847-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  IEC ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Supply Characteristics
    7. 6.7  Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VSUP Pin
      2. 8.3.2  VCC1 Regulator
      3. 8.3.3  VCC2 Regulator
        1. 8.3.3.1 VCC2 Short to Battery Protection
      4. 8.3.4  nRST Pin
      5. 8.3.5  VEXCC Regulator
      6. 8.3.6  CAN FD Transceiver
        1. 8.3.6.1 Driver and Receiver Function
        2. 8.3.6.2 CAN Bus Biasing
      7. 8.3.7  LIN Transceiver
        1. 8.3.7.1 LIN Transmitter Characteristics
        2. 8.3.7.2 LIN Receiver Characteristics
        3. 8.3.7.3 LIN Termination
      8. 8.3.8  GND
      9. 8.3.9  LIMP Pin
      10. 8.3.10 High-side Switches (HSS1- HSS4)
      11. 8.3.11 WAKE1, WAKE2 and WAKE3/DIR Pins
        1. 8.3.11.1 WAKE Pins Alternate Configurations
          1. 8.3.11.1.1 VBAT monitoring
            1. 8.3.11.1.1.1 Interaction Between WAKE1_SENSE/OV_WAKE12SW_DIS and HSS4 Function in Normal Mode
          2. 8.3.11.1.2 Direct Drive
      12. 8.3.12 SDO Pin
      13. 8.3.13 nCS Pin
      14. 8.3.14 SCK Pin
      15. 8.3.15 SDI Pin
      16. 8.3.16 Interrupt Function (nINT)
      17. 8.3.17 SW Pin
      18. 8.3.18 GFO Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Init Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Standby Mode
      4. 8.4.4 Restart Mode
      5. 8.4.5 Fail-Safe Mode
        1. 8.4.5.1 SBC Faults
        2. 8.4.5.2 CAN Transceiver Faults
        3. 8.4.5.3 LIN Transceiver Faults ( TCAN2847x-Q1)
      6. 8.4.6 Sleep Mode
      7. 8.4.7 Wake Functions
        1. 8.4.7.1 CAN Bus Wake Using CRXD Request (BWRR) in Sleep Mode
        2. 8.4.7.2 LIN Bus Wake
        3. 8.4.7.3 Local Wake Up (LWU) via WAKEx Input Terminal
          1. 8.4.7.3.1 Static Wake
          2. 8.4.7.3.2 Cyclic Sensing Wake
        4. 8.4.7.4 Cyclic Wake
        5. 8.4.7.5 Direct Drive in Sleep Mode
        6. 8.4.7.6 Selective Wake-up
          1. 8.4.7.6.1 Selective Wake Mode
          2. 8.4.7.6.2 Frame Detection
          3. 8.4.7.6.3 Wake-Up Frame (WUF) Validation
          4. 8.4.7.6.4 WUF ID Validation
          5. 8.4.7.6.5 WUF DLC Validation
          6. 8.4.7.6.6 WUF Data Validation
          7. 8.4.7.6.7 Frame Error Counter
          8. 8.4.7.6.8 CAN FD Frame Tolerance
          9. 8.4.7.6.9 8Mbps Filtering
      8. 8.4.8 Protection Features
        1. 8.4.8.1  Fail-safe Features
          1. 8.4.8.1.1 Sleep Mode Using Sleep Wake Error
        2. 8.4.8.2  Device Reset
        3. 8.4.8.3  Floating Terminals
        4. 8.4.8.4  TXD Dominant Time Out (DTO)
        5. 8.4.8.5  LIN Bus Stuck Dominant System Fault: False Wake Up Lockout
        6. 8.4.8.6  CAN Bus Short Circuit Current Limiting
        7. 8.4.8.7  Thermal Shutdown
        8. 8.4.8.8  Under and Over Voltage Lockout and Unpowered Device
          1. 8.4.8.8.1 Under-voltage
            1. 8.4.8.8.1.1 VSUP and VHSS Under-voltage
            2. 8.4.8.8.1.2 VCC1 Under-voltage
            3. 8.4.8.8.1.3 VCC2 and VEXCC Under-voltage
            4. 8.4.8.8.1.4 VCAN Under-voltage
          2. 8.4.8.8.2 VCC1, VCC2 and VEXCC Over-voltage
          3. 8.4.8.8.3 VCC1, VCC2 and VEXCC Short Circuit
        9. 8.4.8.9  Watchdog
          1. 8.4.8.9.1 Watchdog Error Counter and Action
          2. 8.4.8.9.2 Watchdog SPI Programming
            1. 8.4.8.9.2.1 Watchdog Configuration Registers Lock and Unlock
              1. 8.4.8.9.2.1.1 Watchdog Configuration in SPI Two-byte Mode
          3. 8.4.8.9.3 Watchdog Timing
          4. 8.4.8.9.4 Question and Answer Watchdog
            1. 8.4.8.9.4.1 WD Question and Answer Basic Information
            2. 8.4.8.9.4.2 Question and Answer Register and Settings
            3. 8.4.8.9.4.3 WD Question and Answer Value Generation
              1. 8.4.8.9.4.3.1 Answer Comparison
              2. 8.4.8.9.4.3.2 Sequence of the 2-bit Watchdog Answer Counter
            4. 8.4.8.9.4.4 Question and Answer WD Example
              1. 8.4.8.9.4.4.1 Example Configuration for Desired Behavior
              2. 8.4.8.9.4.4.2 Example of Performing a Question and Answer Sequence
        10. 8.4.8.10 Bus Fault Detection and Communication
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 Cyclic Redundancy Check
        2. 8.5.1.2 Chip Select Not (nCS):
        3. 8.5.1.3 SPI Clock Input (SCK):
        4. 8.5.1.4 SPI Data Input (SDI):
        5. 8.5.1.5 SPI Data Output (SDO):
      2. 8.5.2 EEPROM
  10. 9 Registers
    1. 9.1 Registers
      1. 9.1.1  DEVICE_ID_y Register (Address = 00h + formula) [reset = xxh]
      2. 9.1.2  REV_ID Register (Address = 08h) [reset = 2Xh]
      3. 9.1.3  SPI_CONFIG Register (Address = 09h) [reset = 00h]
      4. 9.1.4  CRC_CNTL Register (Address = 0Ah) [reset = 00h]
      5. 9.1.5  CRC_POLY_SET (Address = 0Bh) [reset = 00h]
      6. 9.1.6  SBC_CONFIG (Address = 0Ch) [reset = 06h]
      7. 9.1.7  VREG_CONFIG1 (Address = 0Dh) [reset = 80h]
      8. 9.1.8  SBC_CONFIG1 Register (Address = 0Eh) [reset = 01h]
      9. 9.1.9  Scratch_Pad_SPI Register (Address = 0Fh) [reset = 00h]
      10. 9.1.10 CAN_CNTRL_1 Register (Address = 10h) [reset = 04h]
      11. 9.1.11 WAKE_PIN_CONFIG1 Register (Address = 11h) [reset = 00h]
      12. 9.1.12 WAKE_PIN_CONFIG2 Register (Address = 12h) [reset = 02h]
      13. 9.1.13 WD_CONFIG_1 Register (Address = 13h) [reset = 82h]
      14. 9.1.14 WD_CONFIG_2 Register (Address = 14h) [reset = 60h]
      15. 9.1.15 WD_INPUT_TRIG Register (Address = 15h) [reset = 00h]
      16. 9.1.16 WD_RST_PULSE Register (Address = 16h) [reset = 00h]
      17. 9.1.17 FSM_CONFIG Register (Address = 17h) [reset = 00h]
      18. 9.1.18 FSM_CNTR Register (Address = 18h) [reset = 00h]
      19. 9.1.19 DEVICE_CONFIG0 Register (Address = 19h) [reset = 10h]
      20. 9.1.20 DEVICE_CONFIG1 (Address = 1Ah) [reset = 00h]
      21. 9.1.21 DEVICE_CONFIG2 (Address = 1Bh) [reset = 00h]
      22. 9.1.22 SWE_TIMER (Address = 1Ch) [reset = 28h]
      23. 9.1.23 LIN_CNTL (Address = 1Dh) [reset = 20h]
      24. 9.1.24 HSS_CNTL (Address = 1Eh) [reset = 00h]
      25. 9.1.25 PWM1_CNTL1 (Address = 1Fh) [reset = 00h]
      26. 9.1.26 PWM1_CNTL2 (Address = 20h) [reset = 00h]
      27. 9.1.27 PWM1_CNTL3 (Address = 21h) [reset = 00h]
      28. 9.1.28 PWM2_CNTL1 (Address = 22h) [reset = 00h]
      29. 9.1.29 PWM2_CNTL2 (Address = 23h) [reset = 00h]
      30. 9.1.30 PWM2_CNTL3 (Address = 24h) [reset = 00h]
      31. 9.1.31 TIMER1_CONFIG (Address = 25h) [reset = 00h]
      32. 9.1.32 TIMER2_CONFIG (Address = 26h) [reset = 00h]
      33. 9.1.33 RSRT_CNTR (Address = 28h) [reset = 40h]
      34. 9.1.34 nRST_CNTL (Address = 29h) [reset = 2Ch]
      35. 9.1.35 WAKE_PIN_CONFIG3 Register (Address = 2Ah) [reset = E0h]
      36. 9.1.36 WAKE_PIN_CONFIG4 Register (Address = 2Bh) [reset = 22h]
      37. 9.1.37 WD_QA_CONFIG Register (Address = 2Dh) [reset = 0Ah]
      38. 9.1.38 WD_QA_ANSWER Register (Address = 2Eh) [reset = 00h]
      39. 9.1.39 WD_QA_QUESTION Register (Address = 2Fh) [reset = 3Ch]
      40. 9.1.40 SW_ID1 Register (Address = 30h) [reset = 00h]
      41. 9.1.41 SW_ID2 Register (Address = 31h) [reset = 00h]
      42. 9.1.42 SW_ID3 Register (Address = 32h) [reset = 00h]
      43. 9.1.43 SW_ID4 Register (Address = 33h) [reset = 00h]
      44. 9.1.44 SW_ID_MASK1 Register (Address = 34h) [reset = 00h]
      45. 9.1.45 SW_ID_MASK2 Register (Address = 35h) [reset = 00h]
      46. 9.1.46 SW_ID_MASK3 Register (Address = 36h) [reset = 00h]
      47. 9.1.47 SW_ID_MASK4 Register (Address = 37h) [reset = 00h]
      48. 9.1.48 SW_ID_MASK_DLC Register (Address = 38h) [reset = 00h]
      49. 9.1.49 DATA_y Register (Address = 39h + formula) [reset = 00h]
      50. 9.1.50 SW_RSVD_y Register (Address = 41h + formula) [reset = 00h]
      51. 9.1.51 SW_CONFIG_1 Register (Address = 44h) [reset = 50h]
      52. 9.1.52 SW_CONFIG_2 Register (Address = 45h) [reset = 00h]
      53. 9.1.53 SW_CONFIG_3 Register (Address = 46h) [reset = 1Fh]
      54. 9.1.54 SW_CONFIG_4 Register (Address = 47h) [reset = 00h]
      55. 9.1.55 SW_CONFIG_RSVD_y Register (Address = 48h + formula) [reset = 00h]
      56. 9.1.56 HSS_CNTL2 (Address = 4Dh) [reset = 00h]
      57. 9.1.57 EEPROM_CONFIG (Address = 4Eh) [reset = 00h]
      58. 9.1.58 HSS_CNTL3 (Address = 4Fh) [reset = 00h]
      59. 9.1.59 INT_GLOBAL Register (Address = 50h) [reset = 00h]
      60. 9.1.60 INT_1 Register (Address = 51h) [reset = 00h]
      61. 9.1.61 INT_2 Register (Address = 52h) [reset = 40h]
      62. 9.1.62 INT_3 Register (Address 53h) [reset = 00h]
      63. 9.1.63 INT_CANBUS_1 Register (Address = 54h) [reset = 00h]
      64. 9.1.64 INT_7 (Address = 55h) [reset = 00h]
      65. 9.1.65 INT_EN_1 Register (Address = 56h) [reset = FFh]
      66. 9.1.66 INT_EN_2 Register (Address = 57h) [reset = 7Eh]
      67. 9.1.67 INT_EN_3 Register (Address = 58h) [reset = FEh]
      68. 9.1.68 INT_EN_CANBUS_1 Register (Address = 59h) [reset = BFh]
      69. 9.1.69 INT_4 Register (Address = 5Ah) [reset = 00h]
      70. 9.1.70 INT_6 Register (Address 5Ch) [reset = 00h]
      71. 9.1.71 INT_EN_4 Register (Address = 5Eh) [reset = DFh]
      72. 9.1.72 INT_EN_6 Register (Address = 60h) [reset = FFh]
      73. 9.1.73 INT_EN_7 Register (Address = 62) [reset = FFh]
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 CAN BUS Loading, Length and Number of Nodes
      2. 10.1.2 CAN Termination
        1. 10.1.2.1 Termination
      3. 10.1.3 Channel Expansion
        1. 10.1.3.1 Channel Expansion for LIN
        2. 10.1.3.2 Channel Expansion for CAN FD
      4. 10.1.4 Device Brownout information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 LTXD Dominant State Timeout Application Note
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 CAN Detailed Design Procedure
        2. 10.2.2.2 LIN Detailed Design Procedures
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 CAN Transceiver Physical Layer Standards:
      2. 11.1.2 LIN Transceiver Physical Layer Standards
      3. 11.1.3 EMC Requirements:
      4. 11.1.4 Conformance Test Requirements:
      5. 11.1.5 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

6.6 Supply Characteristics

Over recommended operating range (unless otherwise noted). Typical values are specified at VSUP = 14V and TJ = 25℃
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BATTERY SUPPLY INPUT (VSUP)
ISUPnormdom Battery supply current device in normal mode with CAN FD and LIN bus dominant Normal mode; CAN and LIN transceivers on and dominant; no external pull-up on LIN node, VEXCC, VCC1 = On with no load, VCC2 ON and connected to VCAN; VSUP = 14V 40 60 mA
ISUPnormrex Battery supply current device in normal mode with CAN FD and LIN bus recessive Normal mode; CAN and LIN transceivers on and recessive; no external pull-up on LIN node; VEXCC, VCC1 On with no load, VCC2 ON and connected to VCAN ; VSUP = 14V 5 7.5 mA
ISUPstbyswo Battery supply current, standby mode with selective wake off Standby mode; selective wake off; VEXCC, VCC1 and VCC2 = On with no load; 6.5V ≤ VSUP ≤ 19V; CAN and LIN transceivers are wake capable and buses - recessive; all HSS and WAKE pins are off, WD off; Long Window has expired  80 150 µA
ISUPstbyswolp Battery supply current, low power standby mode with selective wake off Standby mode; selective wake off; VEXCC, VCC2 = off and VCC1 = On with no load; VSUP=14V; CAN and LIN transceivers are wake capable and buses - recessive; All HSS and WAKE pins are off, Watchdog is off; Tj ≤ 85℃, Long Window has expired 50 70 µA
ISUPslpswo Battery supply current, sleep mode with selective wake off Sleep mode; selective wake off; VEXCC, VCC1 and VCC2 = off; 6.5V ≤ VSUP ≤ 19V; transceivers are wake capable; All HSSx and WAKEx are off; Tj ≤ 85℃ 35 60 µA
ISUPslpswodr Battery supply current, sleep mode with selective wake off and HSS4 direct drive Sleep mode; selective wake off; VEXCC and VCC2 = off; VCC1 = On with no load; 6.5V ≤ VSUP ≤ 18V; CAN and LIN transceivers are wake capable; One HSSx turned on for 120µs every 50ms by WAKE3/DIR pin; All other HSSx and WAKEx are off;  TJ ≤ 25℃(2) 50 60 µA
ISUPslpswodr Battery supply current, sleep mode with selective wake off and HSS4 direct drive Sleep mode; selective wake off; VEXCC and VCC2 = off; VCC1 = On with no load; 6.5V ≤ VSUP ≤ 18V; CAN and LIN transceivers are wake capable; One HSSx turned on for 120µs every 50ms by WAKE3/DIR pin; All other HSSx and WAKEx are off;  TJ ≤ 85℃(3) 60 75 µA
ISUPslpswotrx Battery supply current, sleep mode with selective wake off; LDO's and transceivers off Sleep mode; selective wake off; VEXCC, VCC1 and VCC2 = off; 6.5V ≤ VSUP ≤ 19V; transceivers are off; All HSSx are off; one WAKE pin enabled and grounded or floating;  TJ ≤ 85℃ 18 42 µA
VSUP(PU)R Supply on detection (4) VSUP rising; see Figure 7-18 3.1 3.4 3.7 V
VSUP(PU)F Supply off detection (4) VSUP falling; see Figure 10-8 and Figure 10-9 2.7 3 3.3 V
VSUP(PU)HYS Supply off detection hysteresis (4) 50 550 mV
UVSUP5R Supply undervoltage recovery VSUP rising; see Figure 7-18, Figure 10-8 and Figure 10-9 4.9 5.5 V
UVSUP5F Supply undervoltage detection VSUP falling; see Figure 10-8 and Figure 10-9 4.5 5.1 V
UVSUP5HYS Supply undervoltage detection hysteresis 200 600 mV
UVSUP33R Supply undervoltage recovery VSUP rising; see Figure 7-18, Figure 10-8 and Figure 10-9 3.7 4.4 V
UVSUP33F Supply undervoltage detection VSUP falling; see Figure 10-8 and Figure 10-9 3.55 4.25 V
UVSUP33HYS Supply undervoltage detection hysteresis 50 300 mV
INCREMENTAL CURRENT CONSUMPTION FOR FEATURES
ISUPslpswoact Battery supply current, sleep mode with selective wake on and WUP has taken place on CAN bus - bus active (4) Additional current when selective wake is enabled and bus active; VEXCC, VCC1 and VCC2 = off; LIN in wake capable or off 480 550 µA
ISUPHSSNOLOAD Incremental battery supply current for each HSS. (3)  One HSS = On but no load, other HSS off, TJ ≤ 85℃ 35 60 µA
ISUPCANBIAS Additional current consumption when CAN outputs are in automatic bias (before tSILENCE expires) Sleep or Standby mode before tSILENCE expires VSUP =14V; TJ ≤ 85℃  65 75 µA
ISUPWD Incremental battery supply current when watchdog is enabled for Window or Q&A Standby mode; selective wake off; VEXCC, VCC2 = off and VCC1 = On with no load; VSUP 14V; CAN and LIN transceivers are wake capable and buses - recessive; All HSS and WAKE pins are off, Watchdog is enabled (Window, Q&A), TJ ≤ 85℃ 45 55 µA
ISUPWDTO Incremental battery supply current when Timeout watchdog is enabled. Standby mode; selective wake off; VEXCC, VCC2 = off and VCC1 = On with no load; VSUP 14V; CAN and LIN transceivers are wake capable and buses - recessive; All HSS and WAKE pins are off, Watchdog is enabled (Timeout), TJ ≤ 85℃ 2 2.5 µA
ISUPwake Incremental battery supply current for each WAKEx pin when enabled WAKEx pin enabled, VSUP=14V, TJ ≤ 85℃ 1 2 µA
ISUPCS-WK Incremental battery current when cyclic sensing wake is enabled in Sleep mode Sleep mode; cyclic sensing wake enabled, VSUP=14V, TJ  ≤ 85℃, TIMERx with ON width = 1ms,  period = 100ms 5 8 µA
IEXCCslp Incremental battery supply current draw when VEXCC is enabled Sleep mode; VEXCC enabled in stand-alone configuration and no load; includes current into VSUP, VEXMON, VEXCTRL and VEXCC  pins. TJ ≤ 85℃ 40 60 µA
VHSS
IHSSNOLOAD Additional current draw for each HSS turned ON (3) For each HSS turned ON,  No load on HSS output 100 140 µA
UVHSSR High-side switches supply undervoltage recovery VHSS rising 4.6 4.9 V
UVHSSF High-side switches supply undervoltage detection; High-side switches turn-off if HSS_UV_SD_DIS = 0b VHSS falling 4.4 4.7 V
UVHSSHYS High-side switches supply undervoltage detection hysteresis 100 mV
OVHSSR VHSS over-voltage rising threshold; High-side switches turn-off if HSS_OV_SD_DIS = 0b VHSS rising 20 22 V
OVHSSF VHSS over-voltage falling threshold;  VHSS must be below this threshold to enable the high-side switches again  VHSS falling 18.8 21.2 V
OVHSSHYS VHSS over-voltage threshold hysteresis 800 1200 mV
VCC1 REGULATOR
VCC15 Regulated output VSUP = 5.5V to 28V, ICC1 = 1 to 250mA 4.9 5 5.1 V
VCC133 Regulated output VSUP = 5.5V to 28V, ICC1 = 1 to 250mA 3.234 3.3 3.366 V
ICC1SINK VCC1 current sink capability VSUP = 14V and register 8'h0D[3] = 0b –17 –11 –7 µA
VSUP = 14V and register 8'h0D[3] = 1b –155 –112 –75 µA
ICC1LIM VCC1 output current limit VCC1 short to ground 300 750 mA
UVCC15RPR VCC1 undervoltage recovery threshold pre-warning VCC1 rising 4.65 4.9 V
UVCC15FPR VCC1 undervoltage detection threshold pre-warning VCC1 falling 4.55 4.8 V
UVCC15PRHYS Undervoltage pre-warning 5V LDO hysteresis 70 130 mV
UVCC15R1 VCC1 undervoltage recovery threshold 1 VCC1 rising, Register 8'h0E[4:3] = 00b 4.60 4.85 V
UVCC15F1 VCC1 undervoltage detection threshold 1 VCC1 falling, Register 8'h0E[4:3] = 00b 4.50 4.75 V
UVCC15R2 VCC1 undervoltage recovery threshold 2 VCC1 rising, Register 8'h0E[4:3] = 01b 3.85 4.15 V
UVCC15F2 VCC1 undervoltage detection threshold 2 VCC1 falling, Register 8'h0E[4:3] = 01b 3.75 4.05 V
UVCC15R3 VCC1 undervoltage recovery threshold 3 VCC1 rising, Register 8'h0E[4:3] = 10b 3.25 3.55 V
UVCC15F3 VCC1 undervoltage detection threshold 3 VCC1 falling, Register 8'h0E[4:3] = 10b 3.15 3.45 V
UVCC15R4 VCC1 undervoltage recovery, threshold 4 VCC1 rising, Register 8'h0E[4:3] = 11b  4.6 4.85 V
UVCC15F4 VCC1 undervoltage detection, threshold 4 VCC1 falling, Register 8'h0E[4:3] = 11b  3.375 3.675 V
UVCC15HYS4 Undervoltage detection 5V LDO hysteresis, threshold 1-3 Register 8'h0E[4:3] = 11b  1200 mV
UVCC15HYS Undervoltage detection 5V LDO hysteresis, threshold 1-3 Register 8'h0E[4:3] = 00b, 01b or 10b  50 150 mV
UVCC133RPR VCC1 undervoltage recovery threshold pre-warning VCC1 rising 3.1 3.28 V
UVCC133FPR VCC1 undervoltage detection threshold pre-warning VCC1 falling 3 3.2 V
UVCC133PRHYS Undervoltage pre-warning 3.3V LDO hysteresis 60 120 mV
UVCC133R1 VCC1 undervoltage recovery threshold 1 VCC1 rising, Register 8'h0E[4:3] = 00b 3 3.2 V
UVCC133F1 VCC1 undervoltage detection threshold 1 VCC1 falling, Register 8'h0E[4:3] = 00b 2.95 3.15 V
UVCC133R2 VCC1 undervoltage recovery threshold 2 VCC1 rising, Register 8'h0E[4:3] = 01b 2.55 2.75 V
UVCC133F2 VCC1 undervoltage detection threshold 2 VCC1 falling, Register 8'h0E[4:3] = 01b 2.5 2.7 V
UVCC133R3 VCC1 undervoltage recovery threshold 3 VCC1 rising, Register 8'h0E[4:3] = 10b 2.25 2.45 V
UVCC133F3 VCC1 undervoltage detection threshold 3 VCC1 falling, Register 8'h0E[4:3] = 10b 2.2 2.4 V
UVCC133R4 VCC1 undervoltage recovery, threshold 4 VCC1 rising, Register 8'h0E[4:3] = 11b  3 3.2 V
UVCC133F4 VCC1 undervoltage detection, threshold 4 VCC1 falling, Register 8'h0E[4:3] = 11b  2.2 2.4 V
UVCC133HYS4 Undervoltage detection 3.3V LDO hysteresis, threshold 4 Register 8'h0E[4:3] = 11b  800 mV
UVCC133HYS Undervoltage detection 3.3V LDO hysteresis, threshold 1-3  Register 8'h0E[4:3] = 00b, 01b or 10b  30 80 mV
OVCC15R1 Over voltage 5V VCC threshold to enter sleep mode or fail-safe mode Ramp Up, Register 8'h0C[7] = 0b 5.25 5.5 V
OVCC15F1 Over voltage 5V VCC1 threshold Ramp Down, Register 8'h0C[7] = 0b 5.15 5.4 V
OVCC15R2 Over voltage 5V VCC1 threshold to enter sleep mode or fail-safe mode  Ramp Up, Register 8'h0C[7] = 1b 5.47 5.73 V
OVCC15F2 Over voltage 5V VCC1 threshold  Ramp Down, Register 8'h0C[7] = 1b 5.37 5.63 V
OVCC15HYS Over voltage 5V VCC threshold hysteresis 50 150 mV
OVCC133R1 Over voltage 3.3V VCC1 threshold to enter sleep mode or fail-safe mode Ramp up, Register 8'h0C[7] = 0b 3.45 3.6 V
OVCC133F1 Over voltage 3.3V VCC1 threshold Ramp down, Register 8'h0C[7] = 0b 3.4 3.55 V
OVCC133R2 Over voltage 3.3V VCC1 threshold Ramp Up, Register 8'h0C[7] = 1b 3.6 3.8 V
OVCC133F2 Over voltage 3.3V VCC1 threshold to enter sleep mode or fail-safe mode Ramp Down, Register 8'h0C[7] = 1b 3.5 3.7 V
OVCC133HYS1 Over voltage 3.3V VCC threshold hysteresis  OVCC1_SEL Register 8'h0C[7] = 0b 30 50 80 mV
OVCC133HYS2 Over voltage 3.3V VCC threshold hysteresis OVCC1_SEL Register 8'h0C[7] = 1b 70 105 140 mV
VCC15SC VCC1 short circuit threshold to enter sleep mode or fail-safe mode for 5V LDO VSUP ≥ VSUP(PU) 1.7 2.3 V
VCC133SC VCC1 short circuit threshold to enter sleep mode or fail-safe mode for 3.3V LDO VSUP ≥ VSUP(PU) 1.22 1.26 V
V5DROP1VCC1 Dropout voltage (VCC1=5V Configuration) VSUP = 3.5V, ICC1 = 50mA 500 mV
V5DROP2VCC1 Dropout voltage (VCC1=5V Configuration) VSUP = 5V, ICC1 = 150mA 500 mV
V33DROP1VCC1 Dropout voltage (VCC1=3.3V Configuration) VSUP = 3.5V, ICC1 = 50mA 500 mV
VCC2 REGULATOR
VCC2nom Normal operation regulated output VSUP = 14V, ICC2 = 5 to 200mA 4.9 5 5.1 V
VCC2red Reduced operation regulated output VSUP = 8V - 18V; ICC2 = 10µA - 5mA; Tj = 25℃ - 125℃ 4.95 5 5.05 V
ICC2LIM VCC2 output current limit VCC2 = 2.5V 250 650 mA
UVCC2R Undervoltage recovery VCC2 VCC2 rising 4.6 4.9 V
UVCC2F Undervoltage detection VCC2 VCC2 falling 4.5 4.75 V
UVCC2HYS Undervoltage detection VCC2 hysteresis 70 175 mV
OVCC2R Over voltage VCC2 LDO threshold  Ramp Up 5.37 5.63 V
OVCC2F Over voltage VCC2 LDO threshold Ramp Down 5.2 5.5 V
OVCC2HYS Over voltage VCC2 LDO threshold hysteresis 70 175 mV
VCC2SC VCC2 LDO short circuit threshold VSUP ≥ VSUP(PU) 1.7 2.3 V
V5DROP1VCC2 Dropout voltage (5V LDO output, VCC2) VSUP = 3.5V, ICC2 = 50mA 500 mV
V5DROP2VCC2 Dropout voltage (5V LDO output VCC2) VSUP = 5V, ICC2 = 30mA 500 mV
VEXCC REGULATOR
VEXCC18 1.8V PNP output voltage supported 5.5V ≤ VSUP ≤ 28V
10mA ≤ IVCCEXT ≤ 350mA		 1.764 1.8 1.836 V
VEXCC25 2.5V PNP output voltage supported 5.5V ≤ VSUP ≤ 28V
10mA ≤ IVCCEXT ≤ 350mA		 2.45 2.5 2.55 V
VEXCC33 3.3V PNP output voltage supported 5.5V ≤ VSUP ≤ 28V
10mA ≤ IVCCEXT ≤ 350mA		 3.234 3.3 3.366 V
VEXCC5 5V PNP output voltages supported 5.5V ≤ VSUP ≤ 28V
10mA ≤ IVCCEXT ≤ 350mA		 4.9 5 5.1 V
VEXCCACC PNP output voltages accuracy 5.5V ≤ VSUP ≤ 28V
10mA ≤ IVCCEXT ≤ 350mA		 –2 2 %
UVEXCCR VEXCC exiting undervoltage event 5.5V ≤ VSUP ≤ 28V 0.87 0.9 0.93 VEXCC
UVEXCCF VEXCC entering undervoltage event 5.5V ≤ VSUP ≤ 28V 0.81 0.85 0.89 VEXCC
UVEXCCHSY VEXCC entering undervoltage hysteresis 5.5V ≤ VSUP ≤ 28V  30 350 mV
OVEXCCR VEXCC entering overvoltage event 5.5V ≤ VSUP ≤ 28V 1.12 1.15 1.18 VEXCC
OVEXCCF VEXCC exiting overvoltage event 5.5V ≤ VSUP ≤ 28V 1.07 1.1 1.13 VEXCC
OVEXCCHYS VEXCC exiting overvoltage hysteresis 5.5V ≤ VSUP ≤ 28V 45 300 mV
VEXCCSC18 VEXCC short circuit detect for 1.8V and 2.5V 5.5V ≤ VSUP ≤ 28V 1.1 1.26 V
VEXCCSC VEXCC short circuit detect for 3.3V and 5V 5.5V ≤ VSUP ≤ 28V 1.7 2.3 V
IVEXCC Input current on VEXCC VEXCC = 5V, 3.3V, 2.5V and 1.8V 3 10 µA
VVEXCTRL Voltage output on base pin of external PNP 5.5V ≤ VSUP ≤ 28V 28 V
IVEXCTRL Drive current at the base pin of external PNP VVEXCTRL = 13.5V 20 40 60 mA
IVEXCTRLLKG Current on base pin VEXCTRL leakage VVEXCTRL = 13.5V; Tj = 25℃ 5 µA
IVEXMON VEXMON pin input current VEXMON = VSUP 0 3 10 µA
IVEXMONLKG VEXMON pin input  leakage current ext PNP disabled VEXMON = VSUP; Tj = 25℃ 5 µA
VSHUNTTH Output current shunt voltage threshold (1) 0.15 0.44 V
tRLINC-3P3V Current increase regulation reaction time

 VEXCC = 3.3V to 0V, Max IVEXCTRL = 20mA, See Figure 8-8 20 µs
tRLDEC-3P3V Current decrease regulation reaction time VEXCC = 0V to 3.3V, Max IVEXCTRL = 20mA, See Figure 8-8 5 µs
tRLINC-5V Current increase regulation reaction time VEXCC = 5V to 0V; Max IVEXCTRL = 20mA, See Figure 8-8 20 µs
tRLDEC-5V Current decrease regulation reaction time VEXCC = 0V to 5V;  Max IVEXCTRL = 20mA, See Figure 8-8 5 µs
RatioICC3/ICC1 Load sharing ratio ICC3:ICC1 6.0V ≤ VSUP ≤ 28V; 
SBC Normal Mode; LS ratio for a 900mΩ
shunt resistor and total load current of 300mA		 1.4 2 2.6
RatioICC3/ICC1 Load sharing ratio ICC3:ICC1 6.0V ≤ VSUP ≤ 28V; 
SBC Normal Mode; LS ratio for a 4.3Ω
shunt resistor and total load current of 300mA		 0.7 1 1.3
VCAN SUPPLY INPUT
IVCAN Supply current Normal mode: Recessive, VTXD = VCC1 , VEXCC, VCC1 and VCC2 = On with no load 3 5 mA
Normal mode: Dominant, VTXD = 0V, RL = 60Ω and CL = open, typical bus load, VEXCC, VCC1 and VCC2 = On with no load 60 mA
Normal mode: Dominant, VTXD = 0V, RL = 50Ω and CL = open, high bus load, VEXCC, VCC1 and VCC2 = On with no load 65 mA
Normal mode: Dominant with bus fault, VTXD = 0V, CANH = - 25V, RL and CL = open, VEXCC, VCC1 and VCC2 = On with no load 100 mA
UVCANR Supply undervoltage recovery VCAN rising 4.6 4.85 V
UVCANF Supply undervoltage detection VCAN falling 4.5 4.75 V
UVCANHYS VCAN Supply undervoltage detections hysteresis 50 100 150 mV
(1) Threshold at which the current limit starts to operate and is only active when VEXCC is configured for stand-alone configuration
(2) Additional current is consumed for each additional HSS turned on using direct drive
(3) Add IHSSNOLOAD and ISUPHSS to determine the total battery current draw.
(4) Specified by design