SLLSFE8B November   2024  – November 2025 TCAN2845-Q1 , TCAN2847-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  IEC ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Supply Characteristics
    7. 6.7  Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VSUP Pin
      2. 8.3.2  VCC1 Regulator
      3. 8.3.3  VCC2 Regulator
        1. 8.3.3.1 VCC2 Short to Battery Protection
      4. 8.3.4  nRST Pin
      5. 8.3.5  VEXCC Regulator
      6. 8.3.6  CAN FD Transceiver
        1. 8.3.6.1 Driver and Receiver Function
        2. 8.3.6.2 CAN Bus Biasing
      7. 8.3.7  LIN Transceiver
        1. 8.3.7.1 LIN Transmitter Characteristics
        2. 8.3.7.2 LIN Receiver Characteristics
        3. 8.3.7.3 LIN Termination
      8. 8.3.8  GND
      9. 8.3.9  LIMP Pin
      10. 8.3.10 High-side Switches (HSS1- HSS4)
      11. 8.3.11 WAKE1, WAKE2 and WAKE3/DIR Pins
        1. 8.3.11.1 WAKE Pins Alternate Configurations
          1. 8.3.11.1.1 VBAT monitoring
            1. 8.3.11.1.1.1 Interaction Between WAKE1_SENSE/OV_WAKE12SW_DIS and HSS4 Function in Normal Mode
          2. 8.3.11.1.2 Direct Drive
      12. 8.3.12 SDO Pin
      13. 8.3.13 nCS Pin
      14. 8.3.14 SCK Pin
      15. 8.3.15 SDI Pin
      16. 8.3.16 Interrupt Function (nINT)
      17. 8.3.17 SW Pin
      18. 8.3.18 GFO Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Init Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Standby Mode
      4. 8.4.4 Restart Mode
      5. 8.4.5 Fail-Safe Mode
        1. 8.4.5.1 SBC Faults
        2. 8.4.5.2 CAN Transceiver Faults
        3. 8.4.5.3 LIN Transceiver Faults ( TCAN2847x-Q1)
      6. 8.4.6 Sleep Mode
      7. 8.4.7 Wake Functions
        1. 8.4.7.1 CAN Bus Wake Using CRXD Request (BWRR) in Sleep Mode
        2. 8.4.7.2 LIN Bus Wake
        3. 8.4.7.3 Local Wake Up (LWU) via WAKEx Input Terminal
          1. 8.4.7.3.1 Static Wake
          2. 8.4.7.3.2 Cyclic Sensing Wake
        4. 8.4.7.4 Cyclic Wake
        5. 8.4.7.5 Direct Drive in Sleep Mode
        6. 8.4.7.6 Selective Wake-up
          1. 8.4.7.6.1 Selective Wake Mode
          2. 8.4.7.6.2 Frame Detection
          3. 8.4.7.6.3 Wake-Up Frame (WUF) Validation
          4. 8.4.7.6.4 WUF ID Validation
          5. 8.4.7.6.5 WUF DLC Validation
          6. 8.4.7.6.6 WUF Data Validation
          7. 8.4.7.6.7 Frame Error Counter
          8. 8.4.7.6.8 CAN FD Frame Tolerance
          9. 8.4.7.6.9 8Mbps Filtering
      8. 8.4.8 Protection Features
        1. 8.4.8.1  Fail-safe Features
          1. 8.4.8.1.1 Sleep Mode Using Sleep Wake Error
        2. 8.4.8.2  Device Reset
        3. 8.4.8.3  Floating Terminals
        4. 8.4.8.4  TXD Dominant Time Out (DTO)
        5. 8.4.8.5  LIN Bus Stuck Dominant System Fault: False Wake Up Lockout
        6. 8.4.8.6  CAN Bus Short Circuit Current Limiting
        7. 8.4.8.7  Thermal Shutdown
        8. 8.4.8.8  Under and Over Voltage Lockout and Unpowered Device
          1. 8.4.8.8.1 Under-voltage
            1. 8.4.8.8.1.1 VSUP and VHSS Under-voltage
            2. 8.4.8.8.1.2 VCC1 Under-voltage
            3. 8.4.8.8.1.3 VCC2 and VEXCC Under-voltage
            4. 8.4.8.8.1.4 VCAN Under-voltage
          2. 8.4.8.8.2 VCC1, VCC2 and VEXCC Over-voltage
          3. 8.4.8.8.3 VCC1, VCC2 and VEXCC Short Circuit
        9. 8.4.8.9  Watchdog
          1. 8.4.8.9.1 Watchdog Error Counter and Action
          2. 8.4.8.9.2 Watchdog SPI Programming
            1. 8.4.8.9.2.1 Watchdog Configuration Registers Lock and Unlock
              1. 8.4.8.9.2.1.1 Watchdog Configuration in SPI Two-byte Mode
          3. 8.4.8.9.3 Watchdog Timing
          4. 8.4.8.9.4 Question and Answer Watchdog
            1. 8.4.8.9.4.1 WD Question and Answer Basic Information
            2. 8.4.8.9.4.2 Question and Answer Register and Settings
            3. 8.4.8.9.4.3 WD Question and Answer Value Generation
              1. 8.4.8.9.4.3.1 Answer Comparison
              2. 8.4.8.9.4.3.2 Sequence of the 2-bit Watchdog Answer Counter
            4. 8.4.8.9.4.4 Question and Answer WD Example
              1. 8.4.8.9.4.4.1 Example Configuration for Desired Behavior
              2. 8.4.8.9.4.4.2 Example of Performing a Question and Answer Sequence
        10. 8.4.8.10 Bus Fault Detection and Communication
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 Cyclic Redundancy Check
        2. 8.5.1.2 Chip Select Not (nCS):
        3. 8.5.1.3 SPI Clock Input (SCK):
        4. 8.5.1.4 SPI Data Input (SDI):
        5. 8.5.1.5 SPI Data Output (SDO):
      2. 8.5.2 EEPROM
  10. 9 Registers
    1. 9.1 Registers
      1. 9.1.1  DEVICE_ID_y Register (Address = 00h + formula) [reset = xxh]
      2. 9.1.2  REV_ID Register (Address = 08h) [reset = 2Xh]
      3. 9.1.3  SPI_CONFIG Register (Address = 09h) [reset = 00h]
      4. 9.1.4  CRC_CNTL Register (Address = 0Ah) [reset = 00h]
      5. 9.1.5  CRC_POLY_SET (Address = 0Bh) [reset = 00h]
      6. 9.1.6  SBC_CONFIG (Address = 0Ch) [reset = 06h]
      7. 9.1.7  VREG_CONFIG1 (Address = 0Dh) [reset = 80h]
      8. 9.1.8  SBC_CONFIG1 Register (Address = 0Eh) [reset = 01h]
      9. 9.1.9  Scratch_Pad_SPI Register (Address = 0Fh) [reset = 00h]
      10. 9.1.10 CAN_CNTRL_1 Register (Address = 10h) [reset = 04h]
      11. 9.1.11 WAKE_PIN_CONFIG1 Register (Address = 11h) [reset = 00h]
      12. 9.1.12 WAKE_PIN_CONFIG2 Register (Address = 12h) [reset = 02h]
      13. 9.1.13 WD_CONFIG_1 Register (Address = 13h) [reset = 82h]
      14. 9.1.14 WD_CONFIG_2 Register (Address = 14h) [reset = 60h]
      15. 9.1.15 WD_INPUT_TRIG Register (Address = 15h) [reset = 00h]
      16. 9.1.16 WD_RST_PULSE Register (Address = 16h) [reset = 00h]
      17. 9.1.17 FSM_CONFIG Register (Address = 17h) [reset = 00h]
      18. 9.1.18 FSM_CNTR Register (Address = 18h) [reset = 00h]
      19. 9.1.19 DEVICE_CONFIG0 Register (Address = 19h) [reset = 10h]
      20. 9.1.20 DEVICE_CONFIG1 (Address = 1Ah) [reset = 00h]
      21. 9.1.21 DEVICE_CONFIG2 (Address = 1Bh) [reset = 00h]
      22. 9.1.22 SWE_TIMER (Address = 1Ch) [reset = 28h]
      23. 9.1.23 LIN_CNTL (Address = 1Dh) [reset = 20h]
      24. 9.1.24 HSS_CNTL (Address = 1Eh) [reset = 00h]
      25. 9.1.25 PWM1_CNTL1 (Address = 1Fh) [reset = 00h]
      26. 9.1.26 PWM1_CNTL2 (Address = 20h) [reset = 00h]
      27. 9.1.27 PWM1_CNTL3 (Address = 21h) [reset = 00h]
      28. 9.1.28 PWM2_CNTL1 (Address = 22h) [reset = 00h]
      29. 9.1.29 PWM2_CNTL2 (Address = 23h) [reset = 00h]
      30. 9.1.30 PWM2_CNTL3 (Address = 24h) [reset = 00h]
      31. 9.1.31 TIMER1_CONFIG (Address = 25h) [reset = 00h]
      32. 9.1.32 TIMER2_CONFIG (Address = 26h) [reset = 00h]
      33. 9.1.33 RSRT_CNTR (Address = 28h) [reset = 40h]
      34. 9.1.34 nRST_CNTL (Address = 29h) [reset = 2Ch]
      35. 9.1.35 WAKE_PIN_CONFIG3 Register (Address = 2Ah) [reset = E0h]
      36. 9.1.36 WAKE_PIN_CONFIG4 Register (Address = 2Bh) [reset = 22h]
      37. 9.1.37 WD_QA_CONFIG Register (Address = 2Dh) [reset = 0Ah]
      38. 9.1.38 WD_QA_ANSWER Register (Address = 2Eh) [reset = 00h]
      39. 9.1.39 WD_QA_QUESTION Register (Address = 2Fh) [reset = 3Ch]
      40. 9.1.40 SW_ID1 Register (Address = 30h) [reset = 00h]
      41. 9.1.41 SW_ID2 Register (Address = 31h) [reset = 00h]
      42. 9.1.42 SW_ID3 Register (Address = 32h) [reset = 00h]
      43. 9.1.43 SW_ID4 Register (Address = 33h) [reset = 00h]
      44. 9.1.44 SW_ID_MASK1 Register (Address = 34h) [reset = 00h]
      45. 9.1.45 SW_ID_MASK2 Register (Address = 35h) [reset = 00h]
      46. 9.1.46 SW_ID_MASK3 Register (Address = 36h) [reset = 00h]
      47. 9.1.47 SW_ID_MASK4 Register (Address = 37h) [reset = 00h]
      48. 9.1.48 SW_ID_MASK_DLC Register (Address = 38h) [reset = 00h]
      49. 9.1.49 DATA_y Register (Address = 39h + formula) [reset = 00h]
      50. 9.1.50 SW_RSVD_y Register (Address = 41h + formula) [reset = 00h]
      51. 9.1.51 SW_CONFIG_1 Register (Address = 44h) [reset = 50h]
      52. 9.1.52 SW_CONFIG_2 Register (Address = 45h) [reset = 00h]
      53. 9.1.53 SW_CONFIG_3 Register (Address = 46h) [reset = 1Fh]
      54. 9.1.54 SW_CONFIG_4 Register (Address = 47h) [reset = 00h]
      55. 9.1.55 SW_CONFIG_RSVD_y Register (Address = 48h + formula) [reset = 00h]
      56. 9.1.56 HSS_CNTL2 (Address = 4Dh) [reset = 00h]
      57. 9.1.57 EEPROM_CONFIG (Address = 4Eh) [reset = 00h]
      58. 9.1.58 HSS_CNTL3 (Address = 4Fh) [reset = 00h]
      59. 9.1.59 INT_GLOBAL Register (Address = 50h) [reset = 00h]
      60. 9.1.60 INT_1 Register (Address = 51h) [reset = 00h]
      61. 9.1.61 INT_2 Register (Address = 52h) [reset = 40h]
      62. 9.1.62 INT_3 Register (Address 53h) [reset = 00h]
      63. 9.1.63 INT_CANBUS_1 Register (Address = 54h) [reset = 00h]
      64. 9.1.64 INT_7 (Address = 55h) [reset = 00h]
      65. 9.1.65 INT_EN_1 Register (Address = 56h) [reset = FFh]
      66. 9.1.66 INT_EN_2 Register (Address = 57h) [reset = 7Eh]
      67. 9.1.67 INT_EN_3 Register (Address = 58h) [reset = FEh]
      68. 9.1.68 INT_EN_CANBUS_1 Register (Address = 59h) [reset = BFh]
      69. 9.1.69 INT_4 Register (Address = 5Ah) [reset = 00h]
      70. 9.1.70 INT_6 Register (Address 5Ch) [reset = 00h]
      71. 9.1.71 INT_EN_4 Register (Address = 5Eh) [reset = DFh]
      72. 9.1.72 INT_EN_6 Register (Address = 60h) [reset = FFh]
      73. 9.1.73 INT_EN_7 Register (Address = 62) [reset = FFh]
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 CAN BUS Loading, Length and Number of Nodes
      2. 10.1.2 CAN Termination
        1. 10.1.2.1 Termination
      3. 10.1.3 Channel Expansion
        1. 10.1.3.1 Channel Expansion for LIN
        2. 10.1.3.2 Channel Expansion for CAN FD
      4. 10.1.4 Device Brownout information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 LTXD Dominant State Timeout Application Note
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 CAN Detailed Design Procedure
        2. 10.2.2.2 LIN Detailed Design Procedures
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 CAN Transceiver Physical Layer Standards:
      2. 11.1.2 LIN Transceiver Physical Layer Standards
      3. 11.1.3 EMC Requirements:
      4. 11.1.4 Conformance Test Requirements:
      5. 11.1.5 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

6.7 Electrical Characteristics

Over recommended operating range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CAN DRIVER
VCANH(D) Bus output voltage (dominant) CANH See Figure 7-4, VCTXD = 0V,  RL =50Ω to 65Ω,CL = open, RCM = open 3.0 4.26 V
VCANL(D) Bus output voltage (dominant) CANL 0.75 2.01 V
VCANH(R)
VCANL(R)		 Bus output voltage (recessive) See Figure 7-1 and Figure 7-4  VCTXD = VCC1, RL = open (no load), RCM = open 2 2.5 3 V
VCANH(R)
VCANL(R)		 Terminated bus output voltage (recessive) VCTXD = VCC1, RL = 60Ω, Split termination capacitance 4.7nF 2.137 2.887 V
V(DIFF) Maximum differential voltage rating V(DIFF) = VCANH – VCANL –42 42 V
VDIFF(D) Differential output voltage(dominant) on normal bus load See Figure 7-1 and Figure 7-4 , VCTXD = 0V, 50Ω ≤ RL ≤ 65Ω , CL = open, RCM = open 1.5 3 V
VDIFF(D) Differential output voltage(dominant) over extended differential load range See Figure 7-1 and Figure 7-4  VCTXD = 0V, 45Ω ≤ RL ≤ 70Ω, CL = open, RCM = open 1.4 3.3 V
VDIFF(D) Differential output voltage(dominant) on effective resistance during arbitration See Figure 7-1 and Figure 7-4  VCTXD = 0V, RL = 2.24kΩ, CL = open, RCM = open 1.5 5 V
VDIFF(R) Differential output voltage(recessive) See Figure 7-1 and Figure 7-4  , VCTXD = VCC1, RL = 45Ω ≤ RL ≤ 65Ω, CL = open, RCM = open –50 50 mV
See Figure 7-1 and Figure 7-4  VCTXD = VCC1, RL = open (no load), CL = open, RCM = open –50 50 mV
VCANH(INACT) Bus output voltage on CANH with bus biasing inactive See Figure 7-1 and Figure 7-4  , VCTXD = VCC1, RL = open, CL = open, RCM = open –0.1 0.1 V
VCANL(INACT) Bus output voltage on CANL with bus biasing inactive –0.1 0.1 V
VDIFF(INACT) Bus output voltage on CANH - CANL (recessive) with bus biasing inactive –0.2 0.2 V
VSYM Output symmetry (dominant or recessive) (VO(CANH) + VO(CANL))/VCC (9) See Figure 7-1 and Figure 7-4 , RL = 60Ω, CL = open, RCM = open, C1 = 4.7nF, CTXD = 250kHz, 1MHz, 2.5MHz 0.9 1.1 V/V
VSYM_DC Output symmetry (dominant or recessive) (VCC – VO(CANH) – VO(CANL))  See Figure 7-1 and Figure 7-4 , RL = 60Ω, CL = open, RCM = open, C1 = 4.7nF –400 400 mV
ICANH(OS) Short-circuit steady-state output current, dominant See Figure 7-1 and Figure 7-8  –3.0V ≤ VCANH ≤ +18.0V, CANL = open, VCTXD = 0V –100 mA
ICANL(OS)  –3.0V ≤ VCANL ≤ +18.0V, CANH = open, VCTXD = 0V 100 mA
IOS_REC Short-circuit steady-state output current, recessive See Figure 7-1 and Figure 7-8  –42V ≤ VBUS ≤ +42V, VBUS = CANH = CANL –5 5 mA
CAN RECEIVER
VDIFF_RX(D) Receiver dominant state differential input voltage range, bus biasing active –12.0V ≤ VCANL ≤ +12.0V
–12.0V ≤ VCANH ≤ +12.0V See Figure 7-5 and Table 8-3   		 0.9 8 V
VDIFF_RX(R) Receiver recessive state differential input voltage range, bus biasing active –3 0.5 V
VHYS Hysteresis voltage for input-threshold, normal and selective wake modes 135 mV
VDIFF_RX(D_INACT) Receiver dominant state differential input voltage range, bus biasing in-active –12.0V ≤ VCANL ≤ +12.0V
–12.0V ≤ VCANH ≤ +12.0V See Figure 7-5 and Table 8-3		 1.15 8 V
VDIFF_RX(R_INACT) Receiver recessive state differential input voltage range, bus biasing in-active –3 0.4 V
VCM_NORM Common mode range: normal –12 12 V
VCM_STBY Common mode range: standby mode –12 12 V
ILKG(OFF) Power-off (unpowered) bus input leakage current CANH = CANL = 5V, VCAN = VSUP pulled to GND using 0Ω and 47kΩ resistor 5 µA
CI Input capacitance to ground (CANH or CANL)      (9) 20 pF
CID Differential input capacitance   (9) 10 pF
RDIFF_PAS_REC Differential input resistance during passive recessive state VCTXD = VCC1, normal mode: –2.0V ≤ VCANH ≤ +7.0V;
–2.0V ≤ VCANL ≤ +7.0V		 12 100 kΩ
RSE_CANH
RSE_CANL		 Single ended Input resistance during passive recessive state –2.0V ≤ VCANH ≤ +7.0V
–2.0V ≤ VCANL ≤ +7.0V		 6 50 kΩ
mR Input resistance matching: [1 – (RIN(CANH) / RIN(CANL))] × 100% VCANH = VCANL = 5.0V –1 1 %
LIN
VOH HIGH level output voltage(1) LIN recessive, LTXD = high, IO = 0mA, VSUP = 5.5V to 28V 0.85 VSUP
VOL LOW level output voltage(1) LIN dominant, LTXD = low, VSUP = 5.5V to 28V 0.2 VSUP
VIH HIGH level input voltage(1) LIN recessive, LTXD = high, IO = 0mA, VSUP = 5.5V to 28V 0.47 0.6 VSUP
VIL LOW level input voltage(1) LIN dominant, LTXD = low, VSUP = 5.5V to 28V 0.4 0.53 VSUP
VSUP_NON_OP VSUP where impact of recessive LIN bus < 5% (ISO/DIS 17987 Parameter 11) LTXD & LRXD open, VLIN = 5.5V to 45 V, VCC = no load –0.3 40 V
IBUS_LIM Limiting current (ISO/DIS 17987-4 Parameter 12) LTXD = 0V, VLIN = 18V, VSUP = 18V
 		 40 90 200 mA
IBUS_PAS_dom Receiver leakage current, dominant (ISO/DIS 17987 Parameter 13) VLIN = 0V, VSUP = 12V Driver off/recessive;  –1 mA
IBUS_PAS_rec1 Receiver leakage current, recessive (ISO/DIS 17987 Parameter 14) VLIN ≥ VSUP, 5.5V ≤ VSUP ≤ 28V Driver off; 20 µA
IBUS_PAS_rec2 Receiver leakage current, recessive (ISO/DIS 17987 Parameter 14) VLIN = VSUP, Driver off; –5 5 µA
IBUS_NO_GND Leakage current, loss of ground (ISO/DIS 17987 Parameter 15) GND = VSUP, VSUP = 12V, 0V ≤ VLIN ≤ 28V; –1 1 mA
IBUSrec_NO_GND Leakage current, loss of ground LIN bus is in recessive state GND = VSUP, VSUP = 12V = VLIN  V; –100 100 µA
IBUS_NO_BAT Leakage current, loss of supply (ISO/DIS 17987 Parameter 16) 0V ≤ VLIN ≤ 28V, VSUP = GND; 10 µA
VBUSdom Low level input voltage (ISO/DIS 17987 Parameter 17) LIN dominant (including LIN dominant for wake up);  0.4 VSUP
VBUSrec High level input voltage (ISO/DIS 17987 Parameter 18) LIN recessive; 0.6 VSUP
VBUS_CNT Receiver center threshold (ISO/DIS 17987 Parameter 19) VBUS_CNT = (VIL + VIH)/2; 0.475 0.5 0.525 VSUP
VHYS Hysteresis voltage (ISO/DIS 17987 Parameter 20) (2) VHYS = (VIH - VIL); VHYS = (Vth_rec - Vth_dom)(3)  0.07 0.175 VSUP
VSERIAL_DIODE Serial diode LIN terminal pullup path (ISO/DIS 17987 Parameter 21) By design and characterization 0.4 0.7 1.0 V
RLIN Internal pullup resistor to VSUP on LIN (ISO/DIS 17987 Parameter 26) Normal and Standby modes 27.66 35 48 kΩ
IRSLEEP Pull-up current source to VSUP Sleep mode, VSUP = 14V, LIN = GND –13 –10 –7 µA
CLIN,PIN Capacitance of the LIN pin By design and characterization 25 pF
LIMP OUTPUT (OPEN-DRAIN)
VOL Open-drain output voltage (active low) External Pull-up; 4.5V < V < 28V, ILIMP = – 6mA 0.5 1 V
ILKG(LIMP) Output current (inactive) VLIMP = 0V to 28V –2 2 µA
HSS1, HSS2, HSS3, HSS4 (HIGH VOLTAGE OUTPUT)
Rdson HSS output drain-to-source on resistance IO = – 60mA 7 12 Ω
Rdson HSS output drain-to-source on resistance IO = – 60mA, VHSS = 14V, TA = 25℃ 7 Ω
IOC(HSS) HSS overcurrent detection limit VHSS = 14V 150 200 300 mA
IOL(HSS) HSS open load current detection threshold when on and current is falling VHSS = 14V 0.4 3.0 mA
IOLHYS(HSS) HSS open load current hysteresis VHSS = 14V 0.05 0.45 1 mA
Ilkg Leakage current HSS = 0V, Sleep Mode –1 1 µA
tR Output rise time (HSS) 6V ≤ VHSS ≤ 18V, RL = 220 Ω,  20%/80% 0.45 2.5 V/µs
tF Output fall time (HSS) 6V ≤ VHSS ≤ 18V, RL = 220 Ω,  80%/20% 0.45 2.5 V/µs
tHSS_on Switching on delay (HSS) from SPI command to on VHSS = 14V, ILOAD = 60mA, VOUT = 80% of VHSS 30 90 µs
tHSS_off Switching off delay (HSS) from SPI command to off VHSS = 14V, ILOAD = 60mA, VOUT = 20% of VHSS 30 90 µs
tR_DD_SR0 Output rise time for HSS in direct drive mode with slow slew rate option HSS_CNTLx=1000b,
VHSS = 13.5V, RL = 2.2kΩ,  HSSx going from 20% to 80% of VHSS		 1.05 1.3 1.6 V/µs
tF_DD_SR0 Output fall time for HSS in direct drive mode with slow slew rate option HSS_CNTLx=1000b,
VHSS = 13.5V, RL = 2.2kΩ,  HSSx going from 80% to 20% of VHSS		 0.95 1.15 1.4 V/µs
tR_DD_SR1 Output rise time (HSS) for HSS in direct drive mode with fast slew rate option HSS_CNTLx=1001b,
VHSS = 13.5V, RL = 2.2kΩ,  HSSx going from 20% to 80% of VHSS		 2.0 2.4 2.85 V/µs
tF_DD_SR1 Output fall time for HSS in direct drive mode with fast slew rate option HSS_CNTLx=1001b,
VHSS = 13.5V, RL = 2.2kΩ,  HSSx going from 80% to 20% of VHSS		 2.0 2.4 2.85 V/µs
tHSSDD_EN_SR0 Enable time from edge change on WAKE3/DIR when configured for direct drive slow slew rate option HSS_CNTLx=1000b,
VHSS = 13.5V, RL = 2.2kΩ, HSSx = 80% of VHSS		 25 35 42 µs
tHSSDD_DIS_SR0 Disable time from edge change on WAKE3/DIR when configured for direct drive with slow slew rate option HSS_CNTLx=1000b,
VHSS = 13.5V, RL = 2.2kΩ, HSSx = 20% of VHSS		 35 55 65 µs
tHSSDD_EN_SR1 Enable time from edge change on WAKE3/DIR when configured for direct drive with fast slew rate option HSS_CNTLx=1001b,
VHSS = 13.5V, RL = 2.2kΩ, HSSx = 80% of VHSS		 20 30 35 µs
tHSSDD_DIS_SR1 Disable time from edge change on WAKE3/DIR when configured for direct drive with fast slew rate option HSS_CNTLx=1001b,
VHSS = 13.5V, RL = 2.2kΩ, HSSx = 20% of VHSS		 20 33 38 µs
tOCFLTR HSS overcurrent filter time for overcurrent fault indication VHSS = 14V 16 µs
tOLFLTR HSS open load filter time for open load fault indication VHSS = 14V 64 µs
tOCOFF HSS overcurrent shut off time. HSS turns off if overcurrent persists for this duration IO(HSS) > IOC(HSS) 250 350 µs
WAKE1, WAKE2, WAKE3 INPUT TERMINAL (HIGH VOLTAGE INPUT)
VIH High-level input voltage: Sleep, selective wake-up or standby mode, WAKE pin enabled (7) Register setting 00b VCC1 based 0.7 VCC1
Register setting 01b 2.5 3.5 V
Register setting 10b 3.8 5 V
Register setting 11b 5.6 7 V
VIL Low-level input voltage: Sleep, selective wake-up or standby mode, WAKE pin enabled (7) Register setting 00b VCC1 based 0.3 VCC1
Register setting 01b 1.5 2.8 V
Register setting 10b 3.0 4.2 V
Register setting 11b 5 6.3 V
IIL Low-level input current(8) WAKE = 1V 1.2 2.2 µA
ILKG Leakage current when Vbat monitoring enabled VWAKE1 = 4V - 28V  2 4 µA
RDSON On resistance of Vbat switch when Vbat monitoring enabled VWAKE1 = 4V - 28V, switch current = 500µA 155 400 Ω
tWAKE Wake up hold time from a wake edge on WAKE in standby or sleep mode for static sensing. See Figure 8-32 and Figure 8-33 140 µs
tWAKE_INVALID WAKE pin pulses shorter than this is filtered out in standby or sleep mode for static sensing. See Figure 8-32 and Figure 8-33 10 µs
SW INPUT TERMINAL
VIH High-level input voltage: SW VCC1 Present 0.7 VCC1
VIL Low-level input voltage: SW VCC1 Present 0.3 VCC1
VIHSWINT SW pin high-level input voltage when VCC1 is missing for sleep or fail-safe mode Register 8'h0E[1] = 1 and/or 8'h0E[2] = 1 and VCC1missing in sleep or fail-safe mode 1.2 V
VILSWINT SW low-level input voltage when VCC1 is missing for sleep or fail-safe mode Register 8'h0E[1] = 1 and/or 8'h0E[2] = 1 and VCC1missing in sleep or fail-safe mode 0.4 V
IIHSWINT-PD High-level input leakage current for SW pin (active-high) when VCC1 is off VCC1 off, internal pulldown enabled, Vin = 1.5V 18 32 µA
IILSWINT-PD Low-level input leakage current for SW pin (active-high)  when VCC1 is off VCC1 off, internal pulldown enabled, Vin = 0V –1 1 µA
IIHSWINT-PU High-level input leakage current for SW pin (active-low) when VCC1 is off VCC1 off, internal pullup enabled, Vin = 1.5V –60 –20 µA
IILSWINT-PU Low-level input leakage current for SW pin (active-low) when VCC1 is off VCC1 off, internal pullup enabled Vin = 0V –85 –35 µA
IIH High-level input leakage current (SW pullup) Inputs = VCC1 ± 2% –1 1 µA
IIL Low-level input leakage current (SW Pull-up) Inputs = 0V, VCC1 ± 2% –140 –2 µA
IIH High-level input leakage current (SW pulldown) Inputs = VCC1 ± 2% 15 140 µA
IIL Low-level input leakage current (SW Pull-down) Inputs = 0V, VCC1 ± 2% –1 1 µA
Rpu Pull-up resistor (SW pin) The SW pin has pullup resistor configured (SW pin is configured active low) 40 60 80 kΩ
Rpd Pull-down resistor (SW pin) The SW pin has pulldown resistor configured (SW pin is configured active high) 40 60 80 kΩ
ILKG(OFF) Unpowered leakage current Inputs = 5.5V, VCC1 = VSUP = 0V; TJ = -40 to 85 ℃ –1 0 1 µA
SDI, SCK, nCS, CTXD, LTXD INPUT TERMINALS
VIH High-level input voltage 0.7 VCC1
VIL Low-level input voltage 0.3 VCC1
IIH High-level input leakage current (Internal pullup) Inputs = VCC1 ± 2% –1 1 µA
IIH High-level input leakage current (Internal pulldown) Inputs = VCC1 ± 2% 15 140 µA
IIL Low-level input leakage current (Internal Pull-up) Inputs = 0V, VCC1 ± 2% –140 –2 µA
IIL Low-level input leakage current (Internal Pull-down) Inputs = 0V, VCC1 ± 2% –1 1 µA
CIN Input Capacitance at 20MHz 2 10 pF
ILKG(OFF) Unpowered leakage current Inputs = 5.5V, VCC1 = VSUP = 0V; TJ -40 to 85℃ –1 0 1 µA
Rpd Pull-down resistor (SDI, SCK, and SW pins) These pins have a pulldown resistor if configured accordingly. 40 60 80 kΩ
Rpu Pull-up resistor (SDI, SCK, nCS, SW, CTXD and LTXD pins) The SDI, SCK, and SW pins have a pullup resistor if configured accordingly.  nCS, CTXD, and LTXD always have a pullup. 40 60 80 kΩ
CRXD, LRXD, SDO, GFO, nINT OUTPUT TERMINALS
VOH HIGH level output voltage IOH = -2mA 0.8 VCC1
VOL LOW level output voltage IOL = 2mA 0.2 VCC1
ILKG(OFF) Unpowered leakage current VSUP = 0V; VCC1 = 0V; VO = 0V to VCC1 output level of either 3.3V or 5V –5 5 µA
nRST TERMINAL (INPUT/OUTPUT)
VIH High level input switching threshold voltage Based off of internal voltage 2.1 V
VIL Low level input switching threshold voltage Based off of internal voltage 0.8 V
IOL Low-level output current, open drain nRST = 0.4V 1.5   mA
ILKG Leakage current, high-level nRST = VCC1 –5   5 µA
RPU Pull-up resistance (Output pulled up to VCC1) 10 30 50 kΩ
LIN DUTY CYCLE
D1 Duty Cycle 1 (ISO/DIS 17987 Parameter 27 and J2602 Normal battery)(4)(5) THREC(MAX) = 0.744  × VSUP, THDOM(MAX) = 0.581  × VSUP, VSUP = 7V to 18V, tBIT = 50/52µs, D1 = tBUS_rec(min)/(2  × tBIT), (See Figure 7-13, Figure 7-14) 0.396
D2 Duty Cycle 2 (ISO/DIS 17987 Parameter 28 and J2602 Normal battery)(4)(5) THREC(MIN) = 0.422  × VSUP, THDOM(MIN) = 0.284  × VSUP, VSUP = 7.6V to 18V, tBIT = 50/52µs, D2 = tBUS_rec(MAX)/(2  × tBIT) (See Figure 7-13, Figure 7-14) 0.581
D3 Duty Cycle 3 (ISO/DIS 17987 Parameter 29 and J2602 Normal battery)(4)(5) THREC(MAX) = 0.778  × VSUP, THDOM(MAX) = 0.616  × VSUP, VSUP = 7V to 18V, tBIT = 96µs (10.4kbps), D3 = tBUS_rec(min)/(2  × tBIT), (See Figure 7-13, Figure 7-14) 0.417
D4 Duty Cycle 4 (ISO/DIS 17987 Parameter 30 and J2602 Normal battery)(4)(5) THREC(MIN) = 0.389  × VSUP, THDOM(MIN) = 0.251  × VSUP, VSUP = 7.6V to 18V, tBIT = 96µs (10.4kbps), D4 = tBUS_rec(MAX)/(2  × tBIT) (See Figure 7-13, Figure 7-14) 0.59
D1LB Duty Cycle 1
J2602 Low battery (5)(6)		 THREC(MAX) = 0.665  × VSUP, THDOM(MAX) = 0.499  × VSUP, VSUP = 5.5V to 7V, tBIT = 50/52µs, D1LB = tBUS_rec(min)/(2  × tBIT) (See Figure 7-13, Figure 7-14) 0.396
D2LB Duty Cycle 2
J2602 Low battery(5)(6)		 THREC(MIN) = 0.496  × VSUP, THDOM(MIN) = 0.361  × VSUP, VSUP = 6.1V to 7.6V, tBIT = 50/52µs, D2LB = tBUS_rec(MAX)/(2  × tBIT) (See Figure 7-13, Figure 7-14) 0.581
D3LB Duty Cycle 3
J2602 Low battery (5)(6)		 THREC(MAX) = 0.665  × VSUP, THDOM(MAX) = 0.499  × VSUP, VSUP = 5.5V to 7V, tBIT = 96µs, D3LB = tBUS_rec(min)/(2  × tBIT) (See Figure 7-13, Figure 7-14) 0.417
D4LB Duty Cycle 4
J2602 Low battery (5)(6)		 THREC(MIN) = 0.496  × VSUP, THDOM(MIN) = 0.361  × VSUP, VSUP = 6.1V to 7.6V, tBIT = 96µs, D4LB = tBUS_rec(MAX)/(2  × tBIT) (See Figure 7-13, Figure 7-14) 0.59
Tr-d max tREC(MAX) - tDOM(MIN)(5) THREC(MAX) = 0.744  × VSUP, THDOM(MAX) = 0.581  × VSUP, VSUP = 7V to 18V, tBIT = 52µs (19.231kbps), (See Figure 7-13, Figure 7-14) 10.8 µs
Td-r max tDOM(MAX) - tREC(MIN)(5) THREC(MIN) = 0.422  × VSUP, THDOM(MIN) = 0.284  × VSUP, VSUP = 7.6V to 18V, tBIT = 52µs (19.231kbps), (See Figure 7-13, Figure 7-14) 8.4 µs
Tr-d max tREC(MAX) - tDOM(MIN)(5) THREC(MAX) = 0.778  × VSUP, THDOM(MAX) = 0.616  × VSUP, VSUP = 7V to 18V, tBIT = 96µs (10.4kbps), (See Figure 7-13, Figure 7-14) 15.9 µs
Td-r max tDOM(MAX) - tREC(MIN)(5) THREC(MIN) = 0.389  × VSUP, THDOM(MIN) = 0.251  × VSUP, VSUP = 7.6V to 18V, tBIT = 96µs (10.4kbps), (See Figure 7-13, Figure 7-14) 17.28 µs
(1) SAE J2602 loads include: commander: 5.5nF; 4kΩ and for a responder: 5.5nF; 875Ω
(2) VHYS is defined for both ISO 17987 and SAE J2602-1.
(3) VHYS = (Vth_rec - Vth_dom) where Vth_rec  and Vth_dom are the actual voltage values from VBUSrec and VBUSdom
(4) ISO 17987 loads include 1nF; 1kΩ/ 6.8nF; 660Ω/ 10nF; 500Ω; with tBIT values of 50μs and 96μs
(5) SAE J2602 loads include: commander: 5.5nF; 4kΩ/ 889pF; 20kΩ and for a responder: 5.5nF; 875Ω/ 889pF; 900Ω; with tBIT values of 52μs and 96μs
(6) ISO 17987 does not have a low battery specification. Using the ISO 17987 loads, these low battery duty cycle parameters are covered for tBIT values of 50μs and 96μs
(7) Selected using Register 8'h12[1:0] for WAKE1; Register 8'h2B[5:4] for WAKE2; Register 8'h2B[1:0] for WAKE3
(8) Current based off of setting 11b for the WAKEx pin
(9) Specified by design and characterization