SLLSFE8B November   2024  – November 2025 TCAN2845-Q1 , TCAN2847-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  IEC ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Supply Characteristics
    7. 6.7  Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VSUP Pin
      2. 8.3.2  VCC1 Regulator
      3. 8.3.3  VCC2 Regulator
        1. 8.3.3.1 VCC2 Short to Battery Protection
      4. 8.3.4  nRST Pin
      5. 8.3.5  VEXCC Regulator
      6. 8.3.6  CAN FD Transceiver
        1. 8.3.6.1 Driver and Receiver Function
        2. 8.3.6.2 CAN Bus Biasing
      7. 8.3.7  LIN Transceiver
        1. 8.3.7.1 LIN Transmitter Characteristics
        2. 8.3.7.2 LIN Receiver Characteristics
        3. 8.3.7.3 LIN Termination
      8. 8.3.8  GND
      9. 8.3.9  LIMP Pin
      10. 8.3.10 High-side Switches (HSS1- HSS4)
      11. 8.3.11 WAKE1, WAKE2 and WAKE3/DIR Pins
        1. 8.3.11.1 WAKE Pins Alternate Configurations
          1. 8.3.11.1.1 VBAT monitoring
            1. 8.3.11.1.1.1 Interaction Between WAKE1_SENSE/OV_WAKE12SW_DIS and HSS4 Function in Normal Mode
          2. 8.3.11.1.2 Direct Drive
      12. 8.3.12 SDO Pin
      13. 8.3.13 nCS Pin
      14. 8.3.14 SCK Pin
      15. 8.3.15 SDI Pin
      16. 8.3.16 Interrupt Function (nINT)
      17. 8.3.17 SW Pin
      18. 8.3.18 GFO Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Init Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Standby Mode
      4. 8.4.4 Restart Mode
      5. 8.4.5 Fail-Safe Mode
        1. 8.4.5.1 SBC Faults
        2. 8.4.5.2 CAN Transceiver Faults
        3. 8.4.5.3 LIN Transceiver Faults ( TCAN2847x-Q1)
      6. 8.4.6 Sleep Mode
      7. 8.4.7 Wake Functions
        1. 8.4.7.1 CAN Bus Wake Using CRXD Request (BWRR) in Sleep Mode
        2. 8.4.7.2 LIN Bus Wake
        3. 8.4.7.3 Local Wake Up (LWU) via WAKEx Input Terminal
          1. 8.4.7.3.1 Static Wake
          2. 8.4.7.3.2 Cyclic Sensing Wake
        4. 8.4.7.4 Cyclic Wake
        5. 8.4.7.5 Direct Drive in Sleep Mode
        6. 8.4.7.6 Selective Wake-up
          1. 8.4.7.6.1 Selective Wake Mode
          2. 8.4.7.6.2 Frame Detection
          3. 8.4.7.6.3 Wake-Up Frame (WUF) Validation
          4. 8.4.7.6.4 WUF ID Validation
          5. 8.4.7.6.5 WUF DLC Validation
          6. 8.4.7.6.6 WUF Data Validation
          7. 8.4.7.6.7 Frame Error Counter
          8. 8.4.7.6.8 CAN FD Frame Tolerance
          9. 8.4.7.6.9 8Mbps Filtering
      8. 8.4.8 Protection Features
        1. 8.4.8.1  Fail-safe Features
          1. 8.4.8.1.1 Sleep Mode Using Sleep Wake Error
        2. 8.4.8.2  Device Reset
        3. 8.4.8.3  Floating Terminals
        4. 8.4.8.4  TXD Dominant Time Out (DTO)
        5. 8.4.8.5  LIN Bus Stuck Dominant System Fault: False Wake Up Lockout
        6. 8.4.8.6  CAN Bus Short Circuit Current Limiting
        7. 8.4.8.7  Thermal Shutdown
        8. 8.4.8.8  Under and Over Voltage Lockout and Unpowered Device
          1. 8.4.8.8.1 Under-voltage
            1. 8.4.8.8.1.1 VSUP and VHSS Under-voltage
            2. 8.4.8.8.1.2 VCC1 Under-voltage
            3. 8.4.8.8.1.3 VCC2 and VEXCC Under-voltage
            4. 8.4.8.8.1.4 VCAN Under-voltage
          2. 8.4.8.8.2 VCC1, VCC2 and VEXCC Over-voltage
          3. 8.4.8.8.3 VCC1, VCC2 and VEXCC Short Circuit
        9. 8.4.8.9  Watchdog
          1. 8.4.8.9.1 Watchdog Error Counter and Action
          2. 8.4.8.9.2 Watchdog SPI Programming
            1. 8.4.8.9.2.1 Watchdog Configuration Registers Lock and Unlock
              1. 8.4.8.9.2.1.1 Watchdog Configuration in SPI Two-byte Mode
          3. 8.4.8.9.3 Watchdog Timing
          4. 8.4.8.9.4 Question and Answer Watchdog
            1. 8.4.8.9.4.1 WD Question and Answer Basic Information
            2. 8.4.8.9.4.2 Question and Answer Register and Settings
            3. 8.4.8.9.4.3 WD Question and Answer Value Generation
              1. 8.4.8.9.4.3.1 Answer Comparison
              2. 8.4.8.9.4.3.2 Sequence of the 2-bit Watchdog Answer Counter
            4. 8.4.8.9.4.4 Question and Answer WD Example
              1. 8.4.8.9.4.4.1 Example Configuration for Desired Behavior
              2. 8.4.8.9.4.4.2 Example of Performing a Question and Answer Sequence
        10. 8.4.8.10 Bus Fault Detection and Communication
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 Cyclic Redundancy Check
        2. 8.5.1.2 Chip Select Not (nCS):
        3. 8.5.1.3 SPI Clock Input (SCK):
        4. 8.5.1.4 SPI Data Input (SDI):
        5. 8.5.1.5 SPI Data Output (SDO):
      2. 8.5.2 EEPROM
  10. 9 Registers
    1. 9.1 Registers
      1. 9.1.1  DEVICE_ID_y Register (Address = 00h + formula) [reset = xxh]
      2. 9.1.2  REV_ID Register (Address = 08h) [reset = 2Xh]
      3. 9.1.3  SPI_CONFIG Register (Address = 09h) [reset = 00h]
      4. 9.1.4  CRC_CNTL Register (Address = 0Ah) [reset = 00h]
      5. 9.1.5  CRC_POLY_SET (Address = 0Bh) [reset = 00h]
      6. 9.1.6  SBC_CONFIG (Address = 0Ch) [reset = 06h]
      7. 9.1.7  VREG_CONFIG1 (Address = 0Dh) [reset = 80h]
      8. 9.1.8  SBC_CONFIG1 Register (Address = 0Eh) [reset = 01h]
      9. 9.1.9  Scratch_Pad_SPI Register (Address = 0Fh) [reset = 00h]
      10. 9.1.10 CAN_CNTRL_1 Register (Address = 10h) [reset = 04h]
      11. 9.1.11 WAKE_PIN_CONFIG1 Register (Address = 11h) [reset = 00h]
      12. 9.1.12 WAKE_PIN_CONFIG2 Register (Address = 12h) [reset = 02h]
      13. 9.1.13 WD_CONFIG_1 Register (Address = 13h) [reset = 82h]
      14. 9.1.14 WD_CONFIG_2 Register (Address = 14h) [reset = 60h]
      15. 9.1.15 WD_INPUT_TRIG Register (Address = 15h) [reset = 00h]
      16. 9.1.16 WD_RST_PULSE Register (Address = 16h) [reset = 00h]
      17. 9.1.17 FSM_CONFIG Register (Address = 17h) [reset = 00h]
      18. 9.1.18 FSM_CNTR Register (Address = 18h) [reset = 00h]
      19. 9.1.19 DEVICE_CONFIG0 Register (Address = 19h) [reset = 10h]
      20. 9.1.20 DEVICE_CONFIG1 (Address = 1Ah) [reset = 00h]
      21. 9.1.21 DEVICE_CONFIG2 (Address = 1Bh) [reset = 00h]
      22. 9.1.22 SWE_TIMER (Address = 1Ch) [reset = 28h]
      23. 9.1.23 LIN_CNTL (Address = 1Dh) [reset = 20h]
      24. 9.1.24 HSS_CNTL (Address = 1Eh) [reset = 00h]
      25. 9.1.25 PWM1_CNTL1 (Address = 1Fh) [reset = 00h]
      26. 9.1.26 PWM1_CNTL2 (Address = 20h) [reset = 00h]
      27. 9.1.27 PWM1_CNTL3 (Address = 21h) [reset = 00h]
      28. 9.1.28 PWM2_CNTL1 (Address = 22h) [reset = 00h]
      29. 9.1.29 PWM2_CNTL2 (Address = 23h) [reset = 00h]
      30. 9.1.30 PWM2_CNTL3 (Address = 24h) [reset = 00h]
      31. 9.1.31 TIMER1_CONFIG (Address = 25h) [reset = 00h]
      32. 9.1.32 TIMER2_CONFIG (Address = 26h) [reset = 00h]
      33. 9.1.33 RSRT_CNTR (Address = 28h) [reset = 40h]
      34. 9.1.34 nRST_CNTL (Address = 29h) [reset = 2Ch]
      35. 9.1.35 WAKE_PIN_CONFIG3 Register (Address = 2Ah) [reset = E0h]
      36. 9.1.36 WAKE_PIN_CONFIG4 Register (Address = 2Bh) [reset = 22h]
      37. 9.1.37 WD_QA_CONFIG Register (Address = 2Dh) [reset = 0Ah]
      38. 9.1.38 WD_QA_ANSWER Register (Address = 2Eh) [reset = 00h]
      39. 9.1.39 WD_QA_QUESTION Register (Address = 2Fh) [reset = 3Ch]
      40. 9.1.40 SW_ID1 Register (Address = 30h) [reset = 00h]
      41. 9.1.41 SW_ID2 Register (Address = 31h) [reset = 00h]
      42. 9.1.42 SW_ID3 Register (Address = 32h) [reset = 00h]
      43. 9.1.43 SW_ID4 Register (Address = 33h) [reset = 00h]
      44. 9.1.44 SW_ID_MASK1 Register (Address = 34h) [reset = 00h]
      45. 9.1.45 SW_ID_MASK2 Register (Address = 35h) [reset = 00h]
      46. 9.1.46 SW_ID_MASK3 Register (Address = 36h) [reset = 00h]
      47. 9.1.47 SW_ID_MASK4 Register (Address = 37h) [reset = 00h]
      48. 9.1.48 SW_ID_MASK_DLC Register (Address = 38h) [reset = 00h]
      49. 9.1.49 DATA_y Register (Address = 39h + formula) [reset = 00h]
      50. 9.1.50 SW_RSVD_y Register (Address = 41h + formula) [reset = 00h]
      51. 9.1.51 SW_CONFIG_1 Register (Address = 44h) [reset = 50h]
      52. 9.1.52 SW_CONFIG_2 Register (Address = 45h) [reset = 00h]
      53. 9.1.53 SW_CONFIG_3 Register (Address = 46h) [reset = 1Fh]
      54. 9.1.54 SW_CONFIG_4 Register (Address = 47h) [reset = 00h]
      55. 9.1.55 SW_CONFIG_RSVD_y Register (Address = 48h + formula) [reset = 00h]
      56. 9.1.56 HSS_CNTL2 (Address = 4Dh) [reset = 00h]
      57. 9.1.57 EEPROM_CONFIG (Address = 4Eh) [reset = 00h]
      58. 9.1.58 HSS_CNTL3 (Address = 4Fh) [reset = 00h]
      59. 9.1.59 INT_GLOBAL Register (Address = 50h) [reset = 00h]
      60. 9.1.60 INT_1 Register (Address = 51h) [reset = 00h]
      61. 9.1.61 INT_2 Register (Address = 52h) [reset = 40h]
      62. 9.1.62 INT_3 Register (Address 53h) [reset = 00h]
      63. 9.1.63 INT_CANBUS_1 Register (Address = 54h) [reset = 00h]
      64. 9.1.64 INT_7 (Address = 55h) [reset = 00h]
      65. 9.1.65 INT_EN_1 Register (Address = 56h) [reset = FFh]
      66. 9.1.66 INT_EN_2 Register (Address = 57h) [reset = 7Eh]
      67. 9.1.67 INT_EN_3 Register (Address = 58h) [reset = FEh]
      68. 9.1.68 INT_EN_CANBUS_1 Register (Address = 59h) [reset = BFh]
      69. 9.1.69 INT_4 Register (Address = 5Ah) [reset = 00h]
      70. 9.1.70 INT_6 Register (Address 5Ch) [reset = 00h]
      71. 9.1.71 INT_EN_4 Register (Address = 5Eh) [reset = DFh]
      72. 9.1.72 INT_EN_6 Register (Address = 60h) [reset = FFh]
      73. 9.1.73 INT_EN_7 Register (Address = 62) [reset = FFh]
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 CAN BUS Loading, Length and Number of Nodes
      2. 10.1.2 CAN Termination
        1. 10.1.2.1 Termination
      3. 10.1.3 Channel Expansion
        1. 10.1.3.1 Channel Expansion for LIN
        2. 10.1.3.2 Channel Expansion for CAN FD
      4. 10.1.4 Device Brownout information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 LTXD Dominant State Timeout Application Note
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 CAN Detailed Design Procedure
        2. 10.2.2.2 LIN Detailed Design Procedures
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 CAN Transceiver Physical Layer Standards:
      2. 11.1.2 LIN Transceiver Physical Layer Standards
      3. 11.1.3 EMC Requirements:
      4. 11.1.4 Conformance Test Requirements:
      5. 11.1.5 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

10.2 Typical Application

The TCAN284x-Q1 SBC family is typically used in applications with a host microprocessor or FPGA that requires CAN FD and LIN support while using the devices many features like its watchdog, advanced bus fault diagnostics for CAN FD bus and high side switches. Below are typical applications configuration for 3.3V microprocessor applications. These devices work with 3.3V and 5V microprocessors depending upon the value of VCC1. The bus termination is shown for illustrative purposes.

Figure 10-12 shows the TCAN2847x-Q1 with different functions than the previous application.

  • VCC1 providing power to MCU
  • External PNP providing power to a system sensor or second MCU
  • HSS1 and HSS2 connected together to provide higher current to an external component.
  • Cyclic sensing with the WAKE pin and HSS4

TCAN2845-Q1 TCAN2847-Q1 Typical CAN and LIN Applications for TCAN2847x-Q1 with Synchronized High Side SwitchFigure 10-12 Typical CAN and LIN Applications for TCAN2847x-Q1 with Synchronized High Side Switch
TCAN2845-Q1 TCAN2847-Q1 Typical Application Diagram with VBAT monitoring function enabled between WAKE1 and WAKE2 pinsFigure 10-13 Typical Application Diagram with VBAT monitoring function enabled between WAKE1 and WAKE2 pins
Table 10-1 External Component Values
ComponentTypical ValueComments
CAPACITANCE
C222µFDecoupling capacitance to cut-off battery spike, protect from ISO pulses. Can require higher capacitance per application requirements
C3, C4100nF, low ESRDecoupling capacitance, place the capacitance close to the pin of the IC to help with EMC robustness
C54.7µF, low ESRPer application requirements. Min. 1µF required for LDO stability; higher capacitance value recommended here for EMC robustness and help with load transients
C6Refer to microcontroller manual for capacitance requirement per application.To improve stability of supply for microcontroller, not needed for SBC.
C7, C8, C9, CWK122nFRequired for EMC robustness; only needed if WAKE pins are connected to ECU pins
C10100nF, low ESRNeeded for VCAN supply stability, place close to the pin of the IC
C114.7µF, low ESRPer application requirements. Min. 1µF required for LDO stability; higher capacitance value recommended here for EMC robustness and help with load transients
C124.7µF, low ESRPer application requirements. Min. 1µF required for LDO stability; higher capacitance value recommended here for EMC robustness and help with load transients
C134.7nFIf CAN split termination is needed, per OEM requirement
C14220pFLIN termination capacitance
C15, C16100nFOnly needed if HSS is driving ECU-external loads; for EMC protection
RESISTANCES
R1, R3, R53.3kΩSeries resistance to limit the current into WAKE pin and protect from ISO pulses
R2, R4, R63kΩSets the wetting current needed for the switch, as required by the application
R7Vshunt/I_limitΩShunt resistance to set the current limit on VEXCC,

as required by the application

R81kΩLIN leader node termination, if used as a leader node
R9, R1060ΩCAN termination, if needed, per OEM requirement
RWK-VBAT5.1kΩTo limit the current through the battery monitoring switch
RDIV1, RDIV2To limit the voltage at the MCU ADC pin below the Abs Max or ADC input rangePer the MCU ADC pin requirement and max battery voltage requirement
RPROT100ΩOnly if VEXCC is used to power ECU-external sensors (as a global pin): a series resistance, RPROT, is recommended for EMC robustness