SLLSFE8 Data sheet

SLLSFE8B November 2024 – November 2025 TCAN2845-Q1 , TCAN2847-Q1

PRODUCTION DATA

6.9 Switching Characteristics

Over recommended operating range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
TRANSMITTER AND RECEIVER TIMING (CAN FD)
t_{prop(TxD-busrec)}	Propagation delay time, high CTXD to driver recessive	Typical conditions: R_L = 60Ω, C_L = 100pF, R_CM = open CAN_SLOPE_CTRL_EN 8'h0E[7] = 0b; See Figure 7-4		55	90	ns
t_{prop(TxD-busdom)}	Propagation delay time, low CTXD to driver dominant			46	90	ns
t_sk(p)	Pulse skew (\|t_pHR – t_pLD\|)			6	25	ns
t_R/F	Differential output signal rise time:		10	48	85	ns
t_{prop(busrec-RXD)}	Propagation delay time, bus recessive input to high CRXD output	Typical conditions: R_L = 60Ω, C_L = 100pF, R_CM = open CRXD = 15pF CAN_SLOPE_CTRL_EN 8'h0E[7] = 0b; See Figure 7-5		84	115	ns
t_{prop(busdom-RXD)}	Propagation delay time, bus dominant input to RXD low output			55	110	ns
t_LOOP	Loop Delay⁽¹⁾	Typical conditions: R_L = 60Ω, C_L = 100pF, C_CRXD = 15pF, 4.5V ≤ VCAN ≤ 5.5V, VCC1 ± 2%, CAN_SLOPE_CTRL_EN 8'h0E[7] = 0b			215	ns
CAN FD SWITCHING CHARACTERISTICS
t_ΔBit(Bus)2M	Transmitted recessive bit width variation at 2Mbps, intended for use with bit rates above 1Mbps up to 2Mbps⁽³⁾	Typical conditions: R_L = 60Ω, C_L = 100pF, C_CRXD = 15pF; CAN_SLOPE_CTRL_EN 8'h0E[7] = 0b See Section 7	-60		25	ns
t_ΔBit(Bus)5M	Transmitted recessive bit width variation at 5Mbps, intended for use with bit rates above 2Mbps up to 5Mbps⁽³⁾		-40		10	ns
t_ΔBit(Bus)8M	Transmitted recessive bit width variation at 5Mbps, intended for use with bit rates above 5Mbps up to 8Mbps⁽³⁾		-45		10	ns
t_ΔBit(RXD)2M	Received recessive bit width variation at 2Mbps⁽⁴⁾	Typical conditions: R_L = 60Ω, C_L = 100pF, C_CRXD = 15pF; CAN_SLOPE_CTRL_EN 8'h0E[7] = 0b See Section 7	-100		50	ns
t_ΔBit(RXD)5M	Received recessive bit width variation at 5Mbps⁽⁴⁾		-70		20	ns
t_ΔBit(RXD)8M	Received recessive bit width variation at 8Mbps⁽⁴⁾		-70		20	ns
t_ΔREC	Receiver Timing symmetry at 2Mbps, intended for use with bit rates above 1Mbps up to 2Mbps	Typical conditions: R_L = 60Ω, C_L = 100pF, C_CRXD = 15pF; CAN_SLOPE_CTRL_EN 8'h0E[7] = 0b See Section 7	–60	–11	35	ns
	Receiver Timing symmetry at 5Mbps, intended for use with bit rates above 2Mbps up to 5Mbps		–30		10	ns
	Receiver Timing symmetry at 8Mbps		–30		10	ns
SWITCHING CHARACTERISTICS (LIN)
t_{rx_pdr} t_{rx_pdf}	Receiver rising/falling propagation delay time (ISO/DIS 17987 Parameter 31)	R_LRXD = 2.4kΩ, C_RXD = 20pF (See Figure 7-14)			6	µs
t_{rs_sym}	Symmetry of receiver propagation delay time Receiver rising propagation delay time (ISO/DIS 17987 Parameter 32)	Rising edge with respect to falling edge, (t_{rx_sym} = t_{rx_pdf} – t_{rx_pdr}), R_RXD = 2.4kΩ, C_LRXD = 20pF ( Figure 7-14)	–2		2	µs
t_LINBUS	LIN wakeup time (minimum dominant time on LIN bus for wakeup)	See Figure 8-31	25	100	150	µs
t_CLEAR	Time to clear false wakeup prevention logic if LIN bus had a bus stuck dominant fault (recessive time on LIN bus to clear bus stuck dominant fault)	See Figure 8-31	10		60	µs
FAST MODE (LIN)
DR	Data Rate	5.5V ≤ VSUP ≤ 18V, R_LIN = 500Ω and C_LIN(bus) = 600pF			200	kbps
t_{rx_pdr} t_{rx_pdf}	Receiver rising/falling propagation delay time (ISO/DIS 17987 Parameter 31)	R_LRXD = 2.4kΩ, C_LRXD = 20pF (See Figure 7-14)			5	µs
t_txr/f	LIN transmitter rise and fall time	5.5V ≤ VSUP ≤ 18V, R_LIN = 500Ω and C_LIN(bus) = 600pF			1.5	µs
SPI SWITCHING CHARACTERISTICS
f_SCK	SCK, SPI clock frequency ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present, if register BYTE_CNT, 09h[3]=1b (two-byte mode)			2	MHz
f_SCK	SCK, SPI clock frequency ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present, if register BYTE_CNT, 09h[3]=0b (single byte mode)			4	MHz
t_SCK	SCK, SPI clock period ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present; See Figure 7-17 if register BYTE_CNT, 09h[3]=0b (single byte mode)	250			ns
t_SCK	SCK, SPI clock period ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present; See Figure 7-17 if register BYTE_CNT, 09h[3]=1b (two-byte mode)	500			ns
t_SCKR	SCK rise time ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present; See Figure 7-16	40			ns
t_SCKF	SCK fall time ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present; See Figure 7-17	40			ns
t_SCKH	SCK, SPI clock high ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present; See Figure 7-17 if register BYTE_CNT, 09h[3]=1b (two-byte mode)	250			ns
t_SCKH	SCK, SPI clock high ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present; See Figure 7-17 if register BYTE_CNT, 09h[3]=0b (single byte mode)	125			ns
t_SCKL	SCK, SPI clock low ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present; See Figure 7-17 if register BYTE_CNT, 09h[3]=1b (two-byte mode)	250			ns
t_SCKL	SCK, SPI clock low ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present; See Figure 7-17 if register BYTE_CNT, 09h[3]=0b (single byte mode)	125			ns
t_nCSS	nCS chip select setup time ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present; See Figure 7-16			100	ns
t_nCSH	nCS chip select hold time ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present; See Figure 7-16			100	ns
t_nCSD	nCS chip select disable time, 1-byte mode OR 2-byte mode with f_SCK ≤ 2MHz ⁽³⁾	Normal and standby modes, Sleep mode - if VCC1 is present; 1-byte mode OR 2-byte mode with f_SCK ≤ 2MHz See Figure 7-17	50			ns
t_SISU	Data in setup time ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present; See Figure 7-17	50			ns
t_SIH	Data in hold time ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present; See Figure 7-17	50			ns
t_SOV	Data out valid ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present; See Figure 7-17			80	ns
t_RSO	SO rise time ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present; See Figure 7-17			40	ns
t_FSO	SO fall time ⁽²⁾	Normal and standby modes, Sleep mode - if VCC1 is present; See Figure 7-17			40	ns

(1) Time span from signal edge on TXD input to next signal edge with same polarity on RXD output, the maximum of delay of both signal edges is to be considered.

(2) Specified by design

(3)

Equation 2.

∆ t_{B i t (B u s)} = t_{B i t (B u s)} - t_{B i t (T X D)}

(4)

Equation 3.

t_{∆ B i t (R X D)} = t_{B i t (R X D)} - t_{B i t (T X D)}