SLUUDO2 September   2026 AM2611 , AM2612 , AM2612-Q1 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Acronyms
  5. 2Introduction
  6. 3Introduction to CPSWSS and ENET-LLD
    1. 3.1 Hardware
    2. 3.2 Software
    3. 3.3 Application Software
      1. 3.3.1 Board and Peripherals Initialization (SYSCFG)
      2. 3.3.2 CPSW Configuration (ENET-LLD)
      3. 3.3.3 Operating System (FreeRTOS or NoRTOS)
      4. 3.3.4 Middleware Stack (LwIP, Arm® Mbed™ Platform TLS, TSN)
      5. 3.3.5 Application Layer
  7. 4Debugging Hardware and Software
    1. 4.1 Hardware Debugging
      1. 4.1.1 Schematic Review Checklist
        1. 4.1.1.1 Management Data Input/Output (MDIO and MDC)
        2. 4.1.1.2 RGMII Interface
      2. 4.1.2 PHY Debug
        1. 4.1.2.1 PHY Bootstrap Settings
        2. 4.1.2.2 Trace Length
        3. 4.1.2.3 Clock Configuration
        4. 4.1.2.4 Mode Settings
        5. 4.1.2.5 IO MUX and SW Switch Settings
        6. 4.1.2.6 PHY Troubleshooting Guides
        7. 4.1.2.7 Custom Pin MUX Settings
      3. 4.1.3 Test Setup
      4. 4.1.4 Software Debugging
        1. 4.1.4.1 Using GEL Scripts in CCS
          1. 4.1.4.1.1 Statistics Using GEL Scripts
          2. 4.1.4.1.2 Statistics Using Expressions
      5. 4.1.5 Debugging Custom Ethernet Software
        1. 4.1.5.1 Debugging Initialization Sequence
        2. 4.1.5.2 PHY Debugging
        3. 4.1.5.3 MAC Port Debugging
        4. 4.1.5.4 TX Path Debugging
        5. 4.1.5.5 Systematic Debugging Checklist
          1. 4.1.5.5.1 RX Path Debugging
          2. 4.1.5.5.2 Multicast or Broadcast Does Not Work, But Unicast Works
    2. 4.2 Custom Hardware Bring-Up Process
      1. 4.2.1 Example 1: CPSW PHY Loopback
        1. 4.2.1.1 Failure: PHY Not Detected or MDIO Bus Not Alive
        2. 4.2.1.2 Failure: TX Packets Transmitted But RX Count = 0
      2. 4.2.2 Example 2: CPSW MAC Loopback Example
        1. 4.2.2.1 Failure: MAC Loopback Initialization Fails
        2. 4.2.2.2 Failure: TX Packets Increase But RX = 0
        3. 4.2.2.3 Failure: Nonzero Error Counters
      3. 4.2.3 Example 3: Enet_Layer2_CPSW and Enet_Layer2_cpsw_switch
        1. 4.2.3.1 Hardware Setup
        2. 4.2.3.2 Failure: Link Never Comes UP
        3. 4.2.3.3 Failure: Link is Up But No Frames Are Received or Transmitted
        4. 4.2.3.4 Failure: RX and TX Counters Increase But Error Rates Are High
      4. 4.2.4 Example 4: Enet_lwip_cpsw_example
        1. 4.2.4.1 Failure: Link Never Comes Up
        2. 4.2.4.2 Failure: Links Up But No IP Address Is Assigned
        3. 4.2.4.3 Failure: Ping Fails Despite Link and IP Address
    3. 4.3 Debugging Packet Forwarding Issues (ALE and Statistics)
      1. 4.3.1 CPSW Statistics Architecture
        1. 4.3.1.1 What Each Block Measures
        2. 4.3.1.2 Counter Reference Tables
          1. 4.3.1.2.1 MAC Port – RX Counters
          2. 4.3.1.2.2 MAC Port – TX Counters
          3. 4.3.1.2.3 MAC Port and Host Port – ALE and FIFO Drop Counters
          4. 4.3.1.2.4 Host Port – ALE Flood and Overrun Counters
          5. 4.3.1.2.5 MAC Port RX Issues
          6. 4.3.1.2.6 MAC Port TX Issues
          7. 4.3.1.2.7 Host Port RX Issues
          8. 4.3.1.2.8 Host Port TX Issues
    4. 4.4 Custom Board Enablement in SYSCFG
    5. 4.5 LwIP Debug Guide
      1. 4.5.1 LwIP Stack Configuration
      2. 4.5.2 lwip_stats
  8. 5Conclusion
  9. 6References
4.3.1.2.6 MAC Port TX Issues

Table 4-18 highlights some issue that can be uncovered by the counter in the MAC port RX path. Frames as placed on the wire by the GMAC. TX error counters reflect half-duplex collision behavior and PHY-level faults. txGoodFrames only increments when a frame exits the MAC without error.

Table 4-18 MAC Port TX Statistical Summary
Scenario Nonzero Counter Root Cause Debug Method Fix | Reference
macStats.txGoodFrames == 0;
host TX is non-zero		 hostPort.aleDrop or hostPort.portMaskDrop The ALE drops frames that originate in the CPU before the frames reach MAC port 1. Read the host port statistics.
Check aleBlockDrop and portMaskDrop.		 Fix the state of the host port ALE or the DA entry portmask (see Host Port – ALE Flood and Overrun Counters).
TX frames disappear;
no ALE drops		 txExcessiveCollFrames 16+ collision retries – severe duplex mismatch with the link partner Read negotiated duplex using ENET_PHY_IOCTL_GET_LINK_STATUS. Force full-duplex on both ends using userLinkCaps.
TX unreliable;
occasional frame loss		 txLateCollFrames Collision after 512-bit window – the cable is too long (> 100m) or there is a duplex mismatch. Check the cable length. Read link mode. Shorten the cable. Force full-duplex.
TX stalls intermittently txCarrierSenseErrors The PHY drops the carrier mid-frame – marginal link or intermittent disconnect. Monitor delta during traffic. Check the state of the PHY link. Replace the cable. Verify the power and reset sequence of the PHY.
TX throughput lower than expected rxPauseFrames (rising) Remote host sending IEEE 802.3x PAUSE frames – flow control active. Check rxPauseFrames delta. Increase the host-side RX buffer depth or disable flow control.
Deferred frames accumulating txDeferredFrames Half-duplex: channel busy, frame deferred. Check if half-duplex was forced intentionally. Switch to full-duplex. Check automatic negotiation.