SLUUDO2 September   2026 AM2611 , AM2612 , AM2612-Q1 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Acronyms
  5. 2Introduction
  6. 3Introduction to CPSWSS and ENET-LLD
    1. 3.1 Hardware
    2. 3.2 Software
    3. 3.3 Application Software
      1. 3.3.1 Board and Peripherals Initialization (SYSCFG)
      2. 3.3.2 CPSW Configuration (ENET-LLD)
      3. 3.3.3 Operating System (FreeRTOS or NoRTOS)
      4. 3.3.4 Middleware Stack (LwIP, Arm® Mbed™ Platform TLS, TSN)
      5. 3.3.5 Application Layer
  7. 4Debugging Hardware and Software
    1. 4.1 Hardware Debugging
      1. 4.1.1 Schematic Review Checklist
        1. 4.1.1.1 Management Data Input/Output (MDIO and MDC)
        2. 4.1.1.2 RGMII Interface
      2. 4.1.2 PHY Debug
        1. 4.1.2.1 PHY Bootstrap Settings
        2. 4.1.2.2 Trace Length
        3. 4.1.2.3 Clock Configuration
        4. 4.1.2.4 Mode Settings
        5. 4.1.2.5 IO MUX and SW Switch Settings
        6. 4.1.2.6 PHY Troubleshooting Guides
        7. 4.1.2.7 Custom Pin MUX Settings
      3. 4.1.3 Test Setup
      4. 4.1.4 Software Debugging
        1. 4.1.4.1 Using GEL Scripts in CCS
          1. 4.1.4.1.1 Statistics Using GEL Scripts
          2. 4.1.4.1.2 Statistics Using Expressions
      5. 4.1.5 Debugging Custom Ethernet Software
        1. 4.1.5.1 Debugging Initialization Sequence
        2. 4.1.5.2 PHY Debugging
        3. 4.1.5.3 MAC Port Debugging
        4. 4.1.5.4 TX Path Debugging
        5. 4.1.5.5 Systematic Debugging Checklist
          1. 4.1.5.5.1 RX Path Debugging
          2. 4.1.5.5.2 Multicast or Broadcast Does Not Work, But Unicast Works
    2. 4.2 Custom Hardware Bring-Up Process
      1. 4.2.1 Example 1: CPSW PHY Loopback
        1. 4.2.1.1 Failure: PHY Not Detected or MDIO Bus Not Alive
        2. 4.2.1.2 Failure: TX Packets Transmitted But RX Count = 0
      2. 4.2.2 Example 2: CPSW MAC Loopback Example
        1. 4.2.2.1 Failure: MAC Loopback Initialization Fails
        2. 4.2.2.2 Failure: TX Packets Increase But RX = 0
        3. 4.2.2.3 Failure: Nonzero Error Counters
      3. 4.2.3 Example 3: Enet_Layer2_CPSW and Enet_Layer2_cpsw_switch
        1. 4.2.3.1 Hardware Setup
        2. 4.2.3.2 Failure: Link Never Comes UP
        3. 4.2.3.3 Failure: Link is Up But No Frames Are Received or Transmitted
        4. 4.2.3.4 Failure: RX and TX Counters Increase But Error Rates Are High
      4. 4.2.4 Example 4: Enet_lwip_cpsw_example
        1. 4.2.4.1 Failure: Link Never Comes Up
        2. 4.2.4.2 Failure: Links Up But No IP Address Is Assigned
        3. 4.2.4.3 Failure: Ping Fails Despite Link and IP Address
    3. 4.3 Debugging Packet Forwarding Issues (ALE and Statistics)
      1. 4.3.1 CPSW Statistics Architecture
        1. 4.3.1.1 What Each Block Measures
        2. 4.3.1.2 Counter Reference Tables
          1. 4.3.1.2.1 MAC Port – RX Counters
          2. 4.3.1.2.2 MAC Port – TX Counters
          3. 4.3.1.2.3 MAC Port and Host Port – ALE and FIFO Drop Counters
          4. 4.3.1.2.4 Host Port – ALE Flood and Overrun Counters
          5. 4.3.1.2.5 MAC Port RX Issues
          6. 4.3.1.2.6 MAC Port TX Issues
          7. 4.3.1.2.7 Host Port RX Issues
          8. 4.3.1.2.8 Host Port TX Issues
    4. 4.4 Custom Board Enablement in SYSCFG
    5. 4.5 LwIP Debug Guide
      1. 4.5.1 LwIP Stack Configuration
      2. 4.5.2 lwip_stats
  8. 5Conclusion
  9. 6References

4.1.2.4 Mode Settings

Master and slave mode determines which device provides the master clock for the physical layer connection.

  • Master PHY uses the internal local oscillator to generate the transmit clock.
  • Slave PHY locks onto the incoming signal from the master using a phase-locked loop (PLL) and recovers the clock to synchronize the individual transmissions.

In gigabit Ethernet, one end of the link must act as master (transmits the clock) and the other as slave (receives and locks to the clock). This configuration can be established through different means.

  • Hardware Strapping or Register Bit Settings: The user can manually force a device to act exclusively as a master or a slave. This is common in automotive Ethernet (like 100BASE-T1) or fixed infrastructure. Basically, if the speed and duplexity is forced then this configuration must be enabled in hardware.
  • Auto-Negotiation Resolution: By default, devices use a priority hierarchy to make decisions. For example, a multiport switch typically takes priority as the master over a single-port network interface card (NIC). If two identical devices connect, these devices use a random seed generator to determine which is the master.

From a SW perspective, this configuration can be done through a SYSCFG extended PHY configuration. For example, the DP83TG721 PHY has this feature of configuring master or slave mode using an extended configuration. The same PHY also has the provision to configure the master or slave mode using HW strapping. More details on these configurations are available in the specific datasheet for the PHYs. The configuration made using the extended configuration is used to set the PMA_CTRL register.

In case you are using a media convertor, the media convertor EVM also has a master or slave jumper which must be set correctly. An example is shown in Figure 4-5 for the DP83TG720/TG721 evaluation module for a 1Gbps media convertor.

AM2612 AM2611 AM2634 AM2632 AM2631 AM263P4 AM263P2 AM263P4-Q1 AM263P2-Q1 AM2612-Q1 AM2634-Q1 AM2632 PHY Jumper Configuration Figure 4-5 PHY Jumper Configuration

Figure 4-6 shows an example for configuring an MDI master or slave configuration using SYSCFG.

AM2612 AM2611 AM2634 AM2632 AM2631 AM263P4 AM263P2 AM263P4-Q1 AM263P2-Q1 AM2612-Q1 AM2634-Q1 AM2632 SYSCFG Setting for MDI Master Figure 4-6 SYSCFG Setting for MDI Master