SWRU626 December   2025 CC3501E , CC3551E

 

  1.   1
  2. 1 Read This First
    1. 1.1 About This Manual
    2. 1.2 Register, Field, and Bit Calls
    3.     Trademarks
  3. 2 Architecture Overview
    1. 2.1  Target Applications
    2. 2.2  Introduction
    3. 2.3  Internal System Diagram
    4. 2.4  Arm Cortex M33
      1. 2.4.1 Processor Core
      2. 2.4.2 SysTick Timer
      3. 2.4.3 Nested Vectored Interrupt Controller
      4. 2.4.4 System Control Block (SCB)
      5. 2.4.5 TI AI instruction extensions
    5. 2.5  Power Management
      1. 2.5.1 VDD_MAIN
      2. 2.5.2 VDD_IO
      3. 2.5.3 VDDSF
      4. 2.5.4 VDD_PA
    6. 2.6  Debug Subsystem (DEBUGSS)
    7. 2.7  Memory Subsystem (MEMSS)
      1. 2.7.1 External Memory Interface
    8. 2.8  Hardware Security Module
    9. 2.9  General Purpose Timers (GPT)
    10. 2.10 Real Time Clock (RTC)
    11. 2.11 Direct Memory Access
    12. 2.12 GPIOs
    13. 2.13 Communication Peripherals
      1. 2.13.1 UART
      2. 2.13.2 I2C
      3. 2.13.3 SPI
      4. 2.13.4 I2S
      5. 2.13.5 SDMMC
      6. 2.13.6 SDIO
      7. 2.13.7 CAN
      8. 2.13.8 ADC
  4. 3  Arm Cortex-M33 Processor
    1. 3.1 Arm Cortex-M33 Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 M33 instantiation parameters
    4. 3.4 Arm Cortex-M33 System Peripheral Details
      1. 3.4.1 Floating Point Unit (FPU)
      2. 3.4.2 Memory Protection Unit (MPU)
      3. 3.4.3 Digital Signal Processing (DSP)
      4. 3.4.4 Security Attribution Unit (SAU)
      5. 3.4.5 System Timer
      6. 3.4.6 Nested Vectored Interrupt Controller
      7. 3.4.7 System Control Block
      8. 3.4.8 System Control Space
    5. 3.5 CPU Sub-System Peripheral Details
      1. 3.5.1 Trace Port Interface Unit (TPIU)
      2. 3.5.2 DAP Bridge and Debug Authentication
      3. 3.5.3 Implementation Defined Attribution Unit (IDAU)
    6. 3.6 Programming Model
      1. 3.6.1 Modes of operation and execution
        1. 3.6.1.1 Security states
        2. 3.6.1.2 Operating modes
        3. 3.6.1.3 Operating states
        4. 3.6.1.4 Privileged access and unprivileged user access
      2. 3.6.2 Instruction set summary
      3. 3.6.3 Memory model
        1. 3.6.3.1 Private Peripheral Bus
        2. 3.6.3.2 Unaligned accesses
      4. 3.6.4 Processor core registers summary
      5. 3.6.5 Exceptions
        1. 3.6.5.1 Exception handling and prioritization
    7. 3.7 TrustZone-M
      1. 3.7.1 Overview
      2. 3.7.2 M33 Configuration
      3. 3.7.3 Description of elements
        1. 3.7.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 3.7.3.1.1 Expected use
    8. 3.8 CC35xx Host MCU Registers
      1. 3.8.1 HOSTMCU_AON Registers
      2. 3.8.2 HOST_MCU Registers
      3. 3.8.3 HOST_MCU_SEC Registers
    9. 3.9 Arm® Cortex®-M33 Registers
      1. 3.9.1  CPU_ROM_TABLE Registers
      2. 3.9.2  TPIU Registers
      3. 3.9.3  DCB Registers
      4. 3.9.4  DIB Registers
      5. 3.9.5  DWT Registers
      6. 3.9.6  FPB Registers
      7. 3.9.7  FPE Registers
      8. 3.9.8  ICB Registers
      9. 3.9.9  ITM Registers
      10. 3.9.10 MPU Registers
      11. 3.9.11 NVIC Registers
      12. 3.9.12 SAU Registers
      13. 3.9.13 SCB Registers
      14. 3.9.14 SYSTIMER Registers
      15. 3.9.15 SYSTICK Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation to HardFault
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Manager
      1. 5.4.1 Introduction
      2. 5.4.2 Interrupts List
      3. 5.4.3 Wakeup Sources
      4. 5.4.4 Shared Peripherals MUX Selector
        1. 5.4.4.1 ADC HW Event Selector Mux
        2. 5.4.4.2 I2S HW Event Selector Mux
        3. 5.4.4.3 PDM HW Event Selector Mux
      5. 5.4.5 Timers MUX Selector Mux
        1. 5.4.5.1 SysTimer0 HW Event Selector Mux
        2. 5.4.5.2 SysTimer1 HW Event Selector Mux
        3. 5.4.5.3 RTC HW Event Selector Mux
      6. 5.4.6 GPTIMERs MUX Selector Mux
        1. 5.4.6.1 GPTIMER0 HW Event Selector Mux
        2. 5.4.6.2 GPTIMER1 HW Event Selector Mux
    5. 5.5 SOC_IC Registers
    6. 5.6 SOC_AON Registers
    7. 5.7 SOC_AAON Registers
  7. 6 Debug Subsystem (DEBUGSS)
    1. 6.1 Introduction
    2. 6.2 Block Diagram
    3. 6.3 Overview
    4. 6.4 Physical Interface
    5. 6.5 Debug Access Ports
    6. 6.6 Debug Features
      1. 6.6.1 Processor Debug
      2. 6.6.2 Breakpoint Unit (BPU)
      3. 6.6.3 Peripheral Debug
    7. 6.7 Behavior in Low Power Modes
    8. 6.8 Debug Access Control
    9. 6.9 SOC_DEBUGSS Registers
  8. 7 Power, Reset, Clock Management
    1. 7.1 Power Management
      1. 7.1.1 Power Supply System
        1. 7.1.1.1 VDD_MAIN
        2. 7.1.1.2 VIO
        3. 7.1.1.3 VDDSF
        4. 7.1.1.4 VPA
      2. 7.1.2 Power States
      3. 7.1.3 Power Domains
      4. 7.1.4 Brownout (BOR)
      5. 7.1.5 Boot Sequence
    2. 7.2 Reset
      1. 7.2.1 Reset Cause
      2. 7.2.2 Watchdog Timer (WDT)
    3. 7.3 Clocks
      1. 7.3.1 Fast Clock
      2. 7.3.2 Slow Clock
        1. 7.3.2.1 Slow Clock Overview
        2. 7.3.2.2 Slow Clock Tree
        3. 7.3.2.3 Slow Clock Boot Process
    4. 7.4 PRCM_AON Registers
    5. 7.5 PRCM_SCRATCHPAD Registers
  9. 8 Memory Subsystem (MEMSS)
    1. 8.1  Introduction
    2. 8.2  SRAM
    3. 8.3  D-Cache
    4. 8.4  Flash
    5. 8.5  PSRAM
    6. 8.6  XiP Memory Access
      1. 8.6.1 OTFDE
      2. 8.6.2 xSPI
      3. 8.6.3 Topology
      4. 8.6.4 µDMA
      5. 8.6.5 Arbiter
    7. 8.7  ICACHE Registers
    8. 8.8  DCACHE Registers
    9. 8.9  OSPI Registers
    10. 8.10 HOST_XIP Registers
  10. 9 Hardware Security Module (HSM)
    1. 9.1 Introduction
    2. 9.2 Overview
    3. 9.3 Mailbox and Register Access Firewall
    4. 9.4 DMA Firewall
    5. 9.5 HSM Key Storage
    6. 9.6 HSM Registers
    7. 9.7 HSM_NON_SEC Registers
    8. 9.8 HSM_SEC Registers
  11. 10Device Boot and Bootloader
    1. 10.1 CC35xx Boot Concept
    2. 10.2 Features
    3. 10.3 Vendor Images Format and Processing
      1. 10.3.1 External Flash Arrangement
      2. 10.3.2 Vendor Images Format
    4. 10.4 Boot Flows
      1. 10.4.1 Application Execution Boot Flow
      2. 10.4.2 Activation Flow
      3. 10.4.3 Initial Programming Flow
      4. 10.4.4 Reprogramming Flow
      5. 10.4.5 Wireless Connectivity Testing Tool Flow
    5. 10.5 Chain of Trust
  12. 11Direct Memory Access (DMA)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Channels Assignment
      2. 11.3.2 Transfer Types
      3. 11.3.3 Addressing Modes
      4. 11.3.4 Transfer Modes
      5. 11.3.5 DMA Aligner Support
      6. 11.3.6 Initiating DMA Transfers
      7. 11.3.7 Stopping DMA Transfers
      8. 11.3.8 Channel Priorities
      9. 11.3.9 DMA Interrupts
    4. 11.4 HOST_DMA Registers
  13. 12One Time Programming (OTP)
  14. 13General Purpose Timers (GPT)
    1. 13.1 Overview
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1  Prescaler
      2. 13.3.2  Counter
      3. 13.3.3  Target
      4. 13.3.4  Channel Input Logic
      5. 13.3.5  Channel Output Logic
      6. 13.3.6  Channel Actions
        1. 13.3.6.1 Period and Pulse Width Measurement
        2. 13.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 13.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 13.3.7  Channel Capture Configuration
      8. 13.3.8  Channel Filters
        1. 13.3.8.1 Setting up the Channel Filters
      9. 13.3.9  Synchronize Multiple GPTimers
      10. 13.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 13.4 Timer Modes
      1. 13.4.1 Quadrature Decoder
      2. 13.4.2 DMA
      3. 13.4.3 IR Generation
      4. 13.4.4 Fault and Park
      5. 13.4.5 Dead-Band
      6. 13.4.6 Dead-Band, Fault and Park
      7. 13.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 13.5 GPTIMER Registers
  15. 14System Timer (SysTimer)
    1. 14.1 Overview
    2. 14.2 Block Diagram
    3. 14.3 Functional Description
      1. 14.3.1 Common Channel Features
        1. 14.3.1.1 Compare Mode
        2. 14.3.1.2 Capture Mode
        3. 14.3.1.3 Additional Channel Arming Methods
      2. 14.3.2 Interrupts and Events
    4. 14.4 SYSRESOURCES Registers
    5. 14.5 SYSTIM Registers
  16. 15Real-Time Clock (RTC)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Interrupts and Events
      1. 15.3.1 Input Event
      2. 15.3.2 Output Event
      3. 15.3.3 Arming and Disarming Channels
    4. 15.4 CAPTURE and COMPARE Configurations
      1. 15.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 15.4.2 CHANNEL 1 - CAPTURE CHANNEL
    5. 15.5 RTC Registers
  17. 16General Purpose Input/Output (GPIOs)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 I/O Mapping and Configuration
      1. 16.3.1 Basic I/O Mapping
      2. 16.3.2 Pin Mapping
    4. 16.4 Edge Detection
    5. 16.5 GPIO
    6. 16.6 I/O Pins
    7. 16.7 Unused Pins
    8. 16.8 IOMUX Registers
  18. 17Universal Asynchronous Receivers/Transmitters (UART)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 UART Functional Description
      1. 17.3.1 Transmit and Receive Logic
      2. 17.3.2 Baud Rate Generation
      3. 17.3.3 FIFO Operation
        1. 17.3.3.1 FIFO Remapping
      4. 17.3.4 Data Transmission
      5. 17.3.5 Flow Control
      6. 17.3.6 IrDA Encoding and Decoding
      7. 17.3.7 Interrupts
      8. 17.3.8 Loopback Operation
    4. 17.4 UART-LIN Specification
      1. 17.4.1 Break transmission in UART mode
      2. 17.4.2 Break reception in UART mode
      3. 17.4.3 Break/Synch transmission in LIN mode
      4. 17.4.4 Break/Synch reception in LIN mode
      5. 17.4.5 Dormant mode operation
      6. 17.4.6 Event signal generation
      7. 17.4.7 Event signal detection when device is in active/idle modes
      8. 17.4.8 Event signal detection when device is in sleep mode
    5. 17.5 Interface to Host DMA
    6. 17.6 Initialization and Configuration
    7. 17.7 UART Registers
  19. 18Serial Peripheral Interface (SPI)
    1. 18.1 Overview
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Signal Description
    3. 18.3 Functional Description
      1. 18.3.1  Clock Control
      2. 18.3.2  FIFO Operation
        1. 18.3.2.1 Transmit FIFO
        2. 18.3.2.2 Repeated Transmit Operation
        3. 18.3.2.3 Receive FIFO
        4. 18.3.2.4 FIFO Flush
      3. 18.3.3  Interrupts
      4. 18.3.4  Data Format
      5. 18.3.5  Delayed Data Sampling
      6. 18.3.6  Chip Select Control
      7. 18.3.7  Command Data Control
      8. 18.3.8  Protocol Descriptions
        1. 18.3.8.1 Motorola SPI Frame Format
        2. 18.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 18.3.8.3 MICROWIRE Frame Format
      9. 18.3.9  CRC Configuration
      10. 18.3.10 Auto CRC Functionality
      11. 18.3.11 SPI Status
      12. 18.3.12 Debug Halt
    4. 18.4 Host DMA Operation
    5. 18.5 Initialization and Configuration
    6. 18.6 SPI Registers
  20. 19Inter-Integrated Circuit (I2C) Interface
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Clock Control
        1. 19.3.1.1 Internal Clock
        2. 19.3.1.2 External Clock
      2. 19.3.2 General Architecture
        1. 19.3.2.1  Start and Stop Conditions
        2. 19.3.2.2  Data Format with 7-Bit Address
        3. 19.3.2.3  Data Format with 10-Bit Addressing
          1. 19.3.2.3.1 Additional 10-Bit Scenarios
        4. 19.3.2.4  Acknowledge
        5. 19.3.2.5  Repeated Start
        6. 19.3.2.6  Clock Stretching
        7. 19.3.2.7  Arbitration
        8. 19.3.2.8  Multi-Controller mode
        9. 19.3.2.9  Glitch Suppression
        10. 19.3.2.10 FIFO Operation
        11. 19.3.2.11 Burst Mode Operation
        12. 19.3.2.12 DMA Operation
        13. 19.3.2.13 Flush Stale Tx Data in Target Mode
          1. 19.3.2.13.1 Recommended Sequence
        14. 19.3.2.14 SMBUS 3.0 Support
          1. 19.3.2.14.1 Quick Command
          2. 19.3.2.14.2 Acknowledge Control
          3. 19.3.2.14.3 Alert Response protocol
          4. 19.3.2.14.4 Address Resolution Protocol
          5. 19.3.2.14.5 Enhanced Acknowledge Control
    4. 19.4 Initialization and Configuration
    5. 19.5 Interrupts
    6. 19.6 I2C Registers
  21. 20Secure Digital Multimedia Card (SDMMC)
    1. 20.1 Introduction
      1. 20.1.1 SDMMC Features
      2. 20.1.2 Integration
    2. 20.2 Functional Description
      1. 20.2.1  SDMMC Functional Modes
        1. 20.2.1.1 SDMMC Connected to an SD Card
        2. 20.2.1.2 Protocol and Data Format
          1. 20.2.1.2.1 Protocol
          2. 20.2.1.2.2 Data Format
      2. 20.2.2  SD Card Feedback
      3. 20.2.3  Resets
        1. 20.2.3.1 Hardware Reset
        2. 20.2.3.2 Software Reset
      4. 20.2.4  Interrupt Requests
        1. 20.2.4.1 Interrupt-Driven Operation
        2. 20.2.4.2 Polling
      5. 20.2.5  DMA Modes
        1. 20.2.5.1 DMA Peripheral Mode Operations
          1. 20.2.5.1.1 DMA Receive Mode
          2. 20.2.5.1.2 DMA Transmit Mode
      6. 20.2.6  Buffer Management
        1. 20.2.6.1 Data Buffer
          1. 20.2.6.1.1 Memory Size and Block Length
          2. 20.2.6.1.2 Data Buffer Status
      7. 20.2.7  Transfer Process
        1. 20.2.7.1 Different Types of Commands
        2. 20.2.7.2 Different Types of Responses
      8. 20.2.8  Transfer or Command Status and Error Reporting
        1. 20.2.8.1 Busy Timeout for R1b, R5b Response Type
        2. 20.2.8.2 Busy Timeout After Write CRC Status
        3. 20.2.8.3 Write CRC Status Timeout
        4. 20.2.8.4 Read Data Timeout
      9. 20.2.9  Auto Command 12 Timings
        1. 20.2.9.1 Auto Command 12 Timings During Write Transfer
        2. 20.2.9.2 Auto Command 12 Timings During Read Transfer
      10. 20.2.10 Transfer Stop
      11. 20.2.11 Output Signals Generation
        1. 20.2.11.1 Generation on Falling Edge of SDMMC Clock
        2. 20.2.11.2 Generation on Rising Edge of SDMMC Clock
      12. 20.2.12 Test Registers
      13. 20.2.13 SDMMC Hardware Status Features
    3. 20.3 Low-Level Programming Models
      1. 20.3.1 SDMMC Initialization Flow
        1. 20.3.1.1 Enable OCP and CLKADPI Clocks
        2. 20.3.1.2 SD Soft Reset Flow
        3. 20.3.1.3 Set SD Default Capabilities
        4. 20.3.1.4 SDMMC Host and Bus Configuration
      2. 20.3.2 Operational Modes Configuration
        1. 20.3.2.1 Basic Operations for SDMMC
        2. 20.3.2.2 Card Detection, Identification, and Selection
    4. 20.4 SDMMC Registers
  22. 21Secure Digital Input/Output (SDIO)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 SDIO Interface Description
      2. 21.3.2 Protocol and Data Format
      3. 21.3.3 I/O Read/Write Command
        1. 21.3.3.1 IO_WR_DIRECT Command (CMD52)
        2. 21.3.3.2 IO_WR_EXTENDED Command (CMD53)
      4. 21.3.4 Reset
      5. 21.3.5 FIFO Operation
        1. 21.3.5.1 Rx FIFO (For Host Write)
        2. 21.3.5.2 Tx FIFO (For Host Read)
      6. 21.3.6 Interrupt Request
        1. 21.3.6.1 External Host IRQ
        2. 21.3.6.2 M33 IRQ
      7. 21.3.7 Transaction Details
        1. 21.3.7.1 Host write to SDIO IP (Rx FIFO)
          1. 21.3.7.1.1 Host write to SDIO IP (Rx FIFO) – Long SW latency case
          2. 21.3.7.1.2 Host write to SDIO IP (Rx FIFO) – CRC Error Case
        2. 21.3.7.2 Host reads from SDIO (TX buffer)
    4. 21.4 SDIO_CORE Registers
    5. 21.5 SDIO_CARD_FN1 Registers
  23. 22Inter-Integrated Circuit Sound (I2S)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  Signal Descriptions
    4. 22.4  Functional Description
      1. 22.4.1 Pin Configuration
      2. 22.4.2 Serial Format Configuration
        1. 22.4.2.1 Register Configuration
      3. 22.4.3 Left-Justified (LJF)
        1. 22.4.3.1 Register Configuration
      4. 22.4.4 Right-Justified (RJF)
        1. 22.4.4.1 Register Configuration
      5. 22.4.5 DSP
        1. 22.4.5.1 Register Configuration
      6. 22.4.6 Clock Configuration
    5. 22.5  Memory Interface
      1. 22.5.1 Sample Word Length
      2. 22.5.2 Padding Mechanism
      3. 22.5.3 Channel Mapping
      4. 22.5.4 Sample Storage in Memory
      5. 22.5.5 DMA Operation
        1. 22.5.5.1 Start-Up
        2. 22.5.5.2 Operation
        3. 22.5.5.3 Shutdown
    6. 22.6  Samplestamp Generator
      1. 22.6.1 Samplestamp Counters
      2. 22.6.2 Start-Up Triggers
      3. 22.6.3 Samplestamp Capture
      4. 22.6.4 Achieving constant audio latency
    7. 22.7  Error Detection
    8. 22.8  Usage
      1. 22.8.1 Start-Up Sequence
      2. 22.8.2 Shutdown Sequence
    9. 22.9  I2S Configuration Guideline
    10. 22.10 I2S Registers
  24. 23Pulse Density Modulation (PDM)
    1. 23.1  Introduction
    2. 23.2  Block Diagram
    3. 23.3  Input Selection
      1. 23.3.1 PDM Data Mode
      2. 23.3.2 Manchester Input Mode
    4. 23.4  CIC Filter
      1. 23.4.1 Filter Design
      2. 23.4.2 Digital Filter Output
      3. 23.4.3 Offset Binary Mode
      4. 23.4.4 Twos-Complement Mode
    5. 23.5  FIFO Organization in Different Modes
      1. 23.5.1 Single Mono Microphone Configuration
        1. 23.5.1.1 24-bit Sample Size
          1. 23.5.1.1.1 32-bit Data Read
        2. 23.5.1.2 16-bit Sample Size
          1. 23.5.1.2.1 32-bit Data Read
          2. 23.5.1.2.2 16-bit Data Read
        3. 23.5.1.3 8-bit Sample Size
          1. 23.5.1.3.1 32-bit Data Read
          2. 23.5.1.3.2 16-bit Data Read
          3. 23.5.1.3.3 8-bit Data Read
      2. 23.5.2 Stereo or Dual Mono Microphone Configuration
        1. 23.5.2.1 24-bit Sample Size
          1. 23.5.2.1.1 32-bit Data Read
        2. 23.5.2.2 16-bit Sample Size
          1. 23.5.2.2.1 32-bit Data Read
          2. 23.5.2.2.2 16-bit Data Read
        3. 23.5.2.3 8-bit Sample Size
          1. 23.5.2.3.1 32-bit Data Read
          2. 23.5.2.3.2 16-bit Data Read
          3. 23.5.2.3.3 8-bit Data Read
      3. 23.5.3 FIFO Threshold Setting
      4. 23.5.4 Reset FIFO
    6. 23.6  Automatic Gain Control (AGC)
      1. 23.6.1 Operation in 2's Complement Format
      2. 23.6.2 Operation in Offset Binary Format
    7. 23.7  Interrupts
    8. 23.8  Clock Select and Control
    9. 23.9  DMA Operation
    10. 23.10 Samplestamp Generator
      1. 23.10.1 Samplestamp Counters
      2. 23.10.2 Start-Up Triggers
      3. 23.10.3 Samplestamp Capture
      4. 23.10.4 Achieving Constant Audio Latency
    11. 23.11 Debug‑Mode Flag Behavior
    12. 23.12 Software Guidelines
    13. 23.13 PDM Registers
  25. 24Analog to Digital Converter (ADC)
    1. 24.1 Overview
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1  ADC Core
      2. 24.3.2  Voltage Reference Options
      3. 24.3.3  Internal Channels
      4. 24.3.4  Resolution Modes
      5. 24.3.5  ADC Clocking
      6. 24.3.6  Power Down Behavior
      7. 24.3.7  Sampling Trigger Sources and Sampling Modes
        1. 24.3.7.1 AUTO Sampling Mode
        2. 24.3.7.2 MANUAL Sampling Mode
      8. 24.3.8  Sampling Period
      9. 24.3.9  Conversion Modes
      10. 24.3.10 ADC Data Format
      11. 24.3.11 Status Register
      12. 24.3.12 ADC Events
        1. 24.3.12.1 Generic Event Publishers (INT_EVENT0 & INT_EVENT1)
        2. 24.3.12.2 DMA Trigger Event Publisher (INT_EVENT2)
        3. 24.3.12.3 Generic Event Subscriber
      13. 24.3.13 Advanced Features
        1. 24.3.13.1 Window Comparator
        2. 24.3.13.2 DMA & FIFO Operation
          1. 24.3.13.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
          2. 24.3.13.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
          3. 24.3.13.2.3 DMA/CPU Operation Summary Matrix
        3. 24.3.13.3 Ad-hoc Single Conversion
    4. 24.4 ADC Registers
  26. 25Controller Area Network (CAN)
    1. 25.1 Introduction
    2. 25.2 Functions
    3. 25.3 DCAN Subsystem
    4. 25.4 DCAN Functional Description
      1. 25.4.1 Operating Modes
        1. 25.4.1.1 Software Initialization
        2. 25.4.1.2 Normal Operation
        3. 25.4.1.3 Restricted Operation Mode
        4. 25.4.1.4 Bus Monitoring Mode
        5. 25.4.1.5 Disabled Automatic Retransmission
          1. 25.4.1.5.1 Frame Transmission in DAR Mode
        6. 25.4.1.6 Power Down (Sleep Mode)
          1. 25.4.1.6.1 DCAN clock stop and wake operations
          2. 25.4.1.6.2 DCAN debug suspend operation
        7. 25.4.1.7 Test Modes
          1. 25.4.1.7.1 External Loop Back Mode
          2. 25.4.1.7.2 Internal Loop Back Mode
      2. 25.4.2 Timestamp Generation
        1. 25.4.2.1 Block Diagram
      3. 25.4.3 Timeout Counter
      4. 25.4.4 Rx Handling
        1. 25.4.4.1 Acceptance Filtering
          1. 25.4.4.1.1 Range Filter
          2. 25.4.4.1.2 Filter for specific IDs
          3. 25.4.4.1.3 Classic Bit Mask Filter
          4. 25.4.4.1.4 Standard Message ID Filtering
          5. 25.4.4.1.5 Extended Message ID Filtering
        2. 25.4.4.2 Rx FIFOs
          1. 25.4.4.2.1 Rx FIFO Blocking Mode
          2. 25.4.4.2.2 Rx FIFO Overwrite Mode
        3. 25.4.4.3 Dedicated Rx Buffers
          1. 25.4.4.3.1 Rx Buffer Handling
        4. 25.4.4.4 Debug on CAN Support
          1. 25.4.4.4.1 Filtering for Debug Messages
          2. 25.4.4.4.2 Debug Message Handling
      5. 25.4.5 Tx Handling
        1. 25.4.5.1 Transmit Pause
        2. 25.4.5.2 Dedicated Tx Buffers
        3. 25.4.5.3 Tx FIFO
        4. 25.4.5.4 Tx Queue
        5. 25.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 25.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 25.4.5.7 Transmit Cancellation
        8. 25.4.5.8 Tx Event Handling
      6. 25.4.6 FIFO Acknowledge Handling
      7. 25.4.7 DCAN Message RAM
        1. 25.4.7.1 Message RAM Configuration
        2. 25.4.7.2 Rx Buffer and FIFO Element
        3. 25.4.7.3 Tx Buffer Element
        4. 25.4.7.4 Tx Event FIFO Element
        5. 25.4.7.5 Standard Message ID Filter Element
        6. 25.4.7.6 Extended Message ID Filter Element
      8. 25.4.8 Interrupt Requests
    5. 25.5 DCAN Wrapper
    6. 25.6 DCAN Clock Enable
    7. 25.7 DCAN Registers
  27. 26Revision History

18.6 SPI Registers

Table 18-2 lists the memory-mapped registers for the SPI registers. All register offset addresses not listed in Table 18-2 should be considered as reserved locations and the register contents should not be modified.

Table 18-2 SPI Registers
OffsetAcronymRegister NameSection
0hDESCModule DescriptionSection 18.6.1
44hIMASKInterrupt MaskSection 18.6.2
48hRISInterrupt Status FlagsSection 18.6.3
4ChMISMasked Interrupt StatusSection 18.6.4
50hISETInterrupt SetSection 18.6.5
54hICLRInterrupt ClearSection 18.6.6
58hIMSETInterrupt Mask SetSection 18.6.7
5ChIMCLRInterrupt Mask ClearSection 18.6.8
60hEMUEmulationSection 18.6.9
100hCTL0SPI Control RegisterSection 18.6.10
104hCTL1SPI ControlSection 18.6.11
108hCLKCFG0Clock Prescaler ConfigurationSection 18.6.12
10ChCLKCFG1Serial Clock ConfigurationSection 18.6.13
110hIFLSFIFO Trigger LevelsSection 18.6.14
114hDMACRDMA ControlSection 18.6.15
118hRXCRCReceive Cyclic Redundancy CheckSection 18.6.16
11ChTXCRCTransmit CRC ValueSection 18.6.17
120hTXFHDR32Header DataSection 18.6.18
124hTXFHDR24Header Data 24-bitSection 18.6.19
128hTXFHDR16Transmit Header UpdateSection 18.6.20
12ChTXFHDR8Transmit Header DataSection 18.6.21
130hTXFHDRCHeader ControlSection 18.6.22
140hRXDATAReceive DataSection 18.6.23
150hTXDATATransmit DataSection 18.6.24
160hSTAStatus RegisterSection 18.6.25
1000hCLKCFGClock EnableSection 18.6.26

Complex bit access types are encoded to fit into small table cells. Table 18-3 shows the codes that are used for access types in this section.

Table 18-3 SPI Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RCR
C		Read
to Clear
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

18.6.1 DESC Register (Offset = 0h) [Reset = 00000000h]

DESC is shown in Table 18-4.

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Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.

Table 18-4 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDR604DhModule identifier used to uniquely identify this IP.
15-12STDIPOFFR1hStandard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)
11-8INSTIDXR0hIP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).
7-4MAJREVR1hMajor revision of IP (0-15).
3-0MINREVR0hMinor revision of IP (0-15).

18.6.2 IMASK Register (Offset = 44h) [Reset = 00000000h]

IMASK is shown in Table 18-5.

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Interrupt mask. This register selects interrupt sources which are allowed to pass from [RIS.*] to [MIS.*] when the corresponding bit-fields are set to 1.

Table 18-5 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXR/W0hDMA Done TX event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
7DMARXR/W0hDMA Done RX event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
6IDLER/W0hSPI Idle event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
5TXEMPTYR/W0hTransmit FIFO Empty event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
4TXR/W0hTransmit FIFO event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
3RXR/W0hReceive FIFO event.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
2RTOUTR/W0hSPI Receive Time-Out event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
1PERR/W0hParity error event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
0RXOVFR/W0hRXFIFO overflow event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask

18.6.3 RIS Register (Offset = 48h) [Reset = 00000000h]

RIS is shown in Table 18-6.

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Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR.*] register bit.

Table 18-6 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXR0hDMA Done event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the TX DMA event inside SPI.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
7DMARXR0hDMA Done event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows handling of the DMA RX event inside SPI.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
6IDLER0hSPI has completed transfers and moved to IDLE mode. This bit is set when [STA.BUSY] goes low.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
5TXEMPTYR0hTransmit FIFO Empty interrupt mask. This interrupt is set when all data in the Transmit FIFO has been moved to the shift register.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
4TXR0hTransmit FIFO event.This interrupt is set if the selected Transmit FIFO level has been reached.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
3RXR0hReceive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
2RTOUTR0hSPI Receive Time-Out event. This interrupt is set if no activity is detected on the input clock line within the time period dictated by RTOUT value. This is applicable only in peripheral mode.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
1PERR0hParity error event. This bit is set if a Parity error has been detected
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
0RXOVFR0hRXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred

18.6.4 MIS Register (Offset = 4Ch) [Reset = 00000000h]

MIS is shown in Table 18-7.

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Masked interrupt status. This register is simply a bitwise AND of the contents of [IMASK.*] and [RIS.*] registers. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR.*] register bit.

Table 18-7 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXR0hMasked DMA Done event for TX.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
7DMARXR0hMasked DMA Done event for RX.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
6IDLER0hMasked SPI IDLE event.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
5TXEMPTYR0hMasked Transmit FIFO Empty event.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
4TXR0hMasked Transmit FIFO event.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
3RXR0hMasked receive FIFO event.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
2RTOUTR0hMasked SPI Receive Time-Out event.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
1PERR0hMasked Parity error event.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
0RXOVFR0hMasked RXFIFO overflow event.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred

18.6.5 ISET Register (Offset = 50h) [Reset = 00000000h]

ISET is shown in Table 18-8.

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Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding [RIS.*] bit also gets set. If the corresponding [IMASK.*] bit is set, then the corresponding [MIS.*] register bit also gets set.

Table 18-8 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXW0hSet DMA Done event for TX.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set Interrupt
7DMARXW0hSet DMA Done event for RX.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set Interrupt
6IDLEW0hSet SPI IDLE event.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set Interrupt
5TXEMPTYW0hSet Transmit FIFO Empty event.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set Interrupt
4TXW0hSet Transmit FIFO event.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set Interrupt
3RXW0hSet Receive FIFO event.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set Interrupt
2RTOUTW0hSet SPI Receive Time-Out Event.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set Interrrupt Mask
1PERW0hSet Parity error event.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set Interrupt
0RXOVFW0hSet RXFIFO overflow event.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set Interrupt

18.6.6 ICLR Register (Offset = 54h) [Reset = 00000000h]

ICLR is shown in Table 18-9.

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Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding [RIS.*] bit also gets cleared. If the corresponding [IMASK.*] bit is set, then the corresponding [MIS.*] register bit also gets cleared.

Table 18-9 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXW0hClear DMA Done event for TX.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Clear Interrupt
7DMARXW0hClear DMA Done event for RX.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Clear Interrupt
6IDLEW0hClear SPI IDLE event.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Clear Interrupt
5TXEMPTYW0hClear Transmit FIFO Empty event.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Clear Interrupt
4TXW0hClear Transmit FIFO event.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Clear Interrupt
3RXW0hClear Receive FIFO event.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Clear Interrupt
2RTOUTW0hClear SPI Receive Time-Out Event.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set Interrrupt Mask
1PERW0hClear Parity error event.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Clear Interrupt
0RXOVFW0hClear RXFIFO overflow event.
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Clear Interrupt

18.6.7 IMSET Register (Offset = 58h) [Reset = 00000000h]

IMSET is shown in Table 18-10.

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Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding [IMASK.*] bit.

Table 18-10 IMSET Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXW0hSet DMA Done for TX event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set interrupt mask
7DMARXW0hSet DMA Done for RX event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set interrupt mask
6IDLEW0hSet SPI IDLE event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set interrupt mask
5TXEMPTYW0hSet Transmit FIFO Empty event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set interrupt mask
4TXW0hSet Transmit FIFO event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set interrupt mask
3RXW0hSet Receive FIFO event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set interrupt mask
2RTOUTW0hSet SPI Receive Time-Out event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set interrupt mask
1PERW0hSet Parity error event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set interrupt mask
0RXOVFW0hSet RXFIFO overflow event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Set interrupt mask

18.6.8 IMCLR Register (Offset = 5Ch) [Reset = 00000000h]

IMCLR is shown in Table 18-11.

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Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding [IMASK.*] bit.

Table 18-11 IMCLR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8DMATXW0hClear DMA Done for TX event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Clear interrupt mask
7DMARXW0hClear DMA Done for RX event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Clear interrupt mask
6IDLEW0hClear SPI IDLE event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Clear interrupt mask
5TXEMPTYW0hClear Transmit FIFO Empty event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Clear interrupt mask
4TXW0hClear Transmit FIFO event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Clear interrupt mask
3RXW0hClear Receive FIFO event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Clear interrupt mask
2RTOUTW0hClear SPI Receive Time-Out event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Clear interrupt mask
1PERW0hClear Parity error event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Clear interrupt mask
0RXOVFW0hClear RXFIFO overflow event mask
  • 0h = NOEFF : Writing 0 has no effect
  • 1h = Clear interrupt mask

18.6.9 EMU Register (Offset = 60h) [Reset = 00000000h]

EMU is shown in Table 18-12.

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Emulation control register. This register controls the behavior of the IP related to core halted input.

Table 18-12 EMU Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0HALTR/W0hHalt control
  • 0h = Free run option. The IP ignores the state of the core halted input.
  • 1h = Freeze option. The IP freezes functionality when the core halted input is asserted, and resumes when it is deasserted. The freeze can either be immediate or after the IP has reached a boundary (end of word boundary, based on DSS configuration) from where it can resume without corruption.

18.6.10 CTL0 Register (Offset = 100h) [Reset = 00000000h]

CTL0 is shown in Table 18-13.

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SPI control register 0

Table 18-13 CTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-18CSSELR/W0hCS select for Multi SPI support 00 - CS0 01 - CS1 10 - CS2 11 - CS3
  • 0h (R/W) = Select CS0
  • 1h (R/W) = Select CS1
  • 2h (R/W) = Select CS2
  • 3h (R/W) = Select CS3
17IDLEPOCIR/W0hThe Idle value of POCI - when TXFIFO is empty and before data is written into TXFIFO - can be controlled by this field.
  • 0h (R/W) = POCI output idle value of '0'
  • 1h (R/W) = POCI outputs idle value of '1'
16GPCRCENR/W0hGeneral purpose CRC enable. This bit enables transmit side CRC unit for general purpose use by software when SPI is disabled (CTL1.EN = 0). This bit must be 0 when SPI is enabled.
  • 0h = DIS : Transmit side CRC unit is not available for general purpose software use
  • 1h = EN : Transmit side CRC unit is available for general purpose software use
15CRCPOLYR/W0hCRC polynomial selection.
  • 0h = Selects 8-bit CCITT CRC polynomial
  • 1h = Selects 16-bit CCITT CRC polynomial
14AUTOCRCR/W0hAuto insert CRC
  • 0h (R/W) = DIS : Do not insert CRC into TXFIFO upon TXFIFO underflow
  • 1h (R/W) = EN : Insert CRC into TXFIFO upon TXFIFO underflow
13CRCENDR/W0hCRC16 Endianness
  • 0h (R/W) = Auto-insertion of CRC16 is most-significant byte first
  • 1h (R/W) = Auto-insertion of CRC16 is least-significant byte first
12CSCLRR/W0hClear shift register counter on CS inactive. This bit is relevant only in the peripheral mode, when MS=0.
  • 0h = DIS : Disable automatic clear of shift register when CS goes inactive.
  • 1h = EN : Enable automatic clear of shift register when CS goes inactive.
11FIFORSTR/W0hThis bit is used to reset transmit and receive FIFO pointers. This bit is auto cleared once the FIFO pointer reset operation is completed.
  • 0h = FIFO pointers reset completed when 0 is read
  • 1h = Trigger FIFO pointers reset when written to 1.
10HWCSNR/W0hHardware controlled chip select (CS) value. When set CS is zero till TX FIFO is empty, as in - a. CS is de-asserted b. All data bytes are transmitted c. CS is asserted
  • 0h (R/W) = DIS : HWCS Disable
  • 1h (R/W) = EN : HWCS Enable
9SPHR/W0hCLKOUT phase (Motorola SPI frame format only). This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture clock edge.
  • 0h = Data is captured on the first clock edge transition.
  • 1h = Data is captured on the second clock edge transition.
8SPOR/W0hCLKOUT polarity (Motorola SPI frame format only).
  • 0h = LO : SPI produces a steady state LOW value on the CLKOUT
  • 1h = HI : SPI produces a steady state HIGH value on the CLKOUT
7RESERVEDR0hReserved
6-5FRFR/W0hFrame format select
  • 0h = Motorola SPI frame format (3 wire mode)
  • 1h = Motorola SPI frame format (4 wire mode)
  • 2h = TI synchronous serial frame format
  • 3h = National Microwire frame format
4RESERVEDR0hReserved
3-0DSSR/W0hData size select. The applicable DSS values for controller mode operation are 0x3 to 0xF and for peripheral mode operation are 0x6 to 0xF. DSS values 0x0 to 0x2 are reserved and must not be used.
  • 3h (R/W) = 4-bits data size
  • 4h (R/W) = 5-bits data size
  • 5h (R/W) = 6-bits data size
  • 6h (R/W) = 7-bits data size
  • 7h (R/W) = 8-bits data size
  • 8h (R/W) = 9-bits data size
  • 9h (R/W) = 10-bits data size
  • Ah (R/W) = 11-bits data size
  • Bh (R/W) = 12-bits data size
  • Ch (R/W) = 13-bits data size
  • Dh (R/W) = 14-bits data size
  • Eh (R/W) = 15-bits data size
  • Fh (R/W) = 16-bits data size

18.6.11 CTL1 Register (Offset = 104h) [Reset = 00000004h]

CTL1 is shown in Table 18-14.

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SPI control register 1

Table 18-14 CTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-24RTOUTR/W0hReceive Timeout (only for Peripheral mode) Defines the number of Clock Cycles before after which the Receive Timeout flag RTOUT is set. The time is calculated using the control register for the clock selection and divider in the Controller mode configuration. A value of 0 disables this function.
23-16REPTXR/W0hCounter to repeat last transfer 0: repeat last transfer is disabled. x: repeat the last transfer with the provided value. The transfer will be started with writing a data into the TX FIFO. Sending the data will be repeated provided value number of times, so the data will be transferred x+1 times in total. The behavior would be as if the data were be written into the TX FIFO as many times as defined by the value here additionally. It can be used to clean a transfer or to pull a certain amount of data by a peripheral.
15-12CDMODER/W0hCommand Data Mode. This bit field value determines the behavior of C/D or CS signal when CDEN = 1. CS pin held low indicates command phase and CS pin held high indicates data phase. When CDMODE = 0x0, the CS pin is always held high during transfer indicating data phase only operation (manual mode). When CDMODE = 0xF, the CS pin is always held low during transfer indicating command phase only operation (manual mode). When CDMODE = 0x1 to 0xE, the CS pin is held low for the number of bytes indicated by CDMODE value for the command phase and held high for the remaining transfers in the data phase (automatic mode). When CDMODE is set to value 0x1 to 0xE, reading CDMODE during operation indicates the remaining bytes to be transferred in the command phase.
  • 0h = Manual mode: Data
  • Fh = Manual mode: Command
11CDENR/W0hCommand/Data mode enable. This feature is applicable only in controller mode and for 8-bit transfers (DSS = 7). The chip select pin is used for command/data signaling in Motorola SPI frame format (3-wire) operation.
  • 0h = DIS : C/D Mode Disable
  • 1h = EN : C/D Mode Enable
10-8RESERVEDR0hReserved
7PBSR/W0hParity bit select
  • 0h = Bit 0 is used for Parity
  • 1h = Bit 1 is used for Parity, Bit 0 is ignored
6PESR/W0hEven parity select.
  • 0h = Odd Parity mode
  • 1h = Even Parity mode
5PENR/W0hParity enable. If enabled the last bit will be used as parity to evaluate the correct reception of the previous bits. In case of parity mismatch the parity error flag PER will be set. This feature is available only in SPI controller mode.
  • 0h = DIS : Disable Parity function
  • 1h = EN : Enable Parity function
4MSBR/W0hMSB first select. Controls the direction of receive and transmit shift register. MSB first configuration (MSB = 1) must be selected when CRC feature is used for SPI communication.
  • 0h = LSB first
  • 1h = MSB first
3PODR/W0hPeripheral data output disable. This bit is relevant only in the peripheral mode, MS=1. In multiple-peripheral systems, it is possible for a SPI controller to broadcast a message to all peripherals in the system while ensuring that only one peripheral drives data onto its serial output line. In such systems the POCI lines from multiple peripherals could be tied together. To operate in such systems, this bit field can be set if the SPI peripheral is not supposed to drive the POCI output.
  • 0h = DIS : SPI can drive the POCI output in peripheral mode.
  • 1h = EN : SPI cannot drive the POCI output in peripheral mode.
2MSR/W1hController or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.EN=0.
  • 0h = PERIPHERAL : Select Peripheral mode
  • 1h = CONTROLLER : Select Controller mode
1LBMR/W0hLoop back mode control
  • 0h = DIS : Disable loopback mode. Normal serial port operation enabled.
  • 1h = EN : Enable loopback mode. Output of transmit serial shifter is connected to input of receive serial shifter internally.
0ENR/W0hSPI enable.
  • 0h = DIS : SPI is disabled
  • 1h = EN : SPI Enabled and released for operation.

18.6.12 CLKCFG0 Register (Offset = 108h) [Reset = 00000000h]

CLKCFG0 is shown in Table 18-15.

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Clock configuration register 0. This register is used to configure the clock prescaler.

Table 18-15 CLKCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0PRESCR/W0hPrescaler configuration
  • 0h = Do not divide clock source
  • 1h = Divide clock source by 2
  • 2h = Divide clock source by 3
  • 3h = Divide clock source by 4
  • 4h = Divide clock source by 5
  • 5h = Divide clock source by 6
  • 6h = Divide clock source by 7
  • 7h = Divide clock source by 8

18.6.13 CLKCFG1 Register (Offset = 10Ch) [Reset = 00000000h]

CLKCFG1 is shown in Table 18-16.

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Clock configuration register 1. This register is used to configure serial clock rate and clock count for delayed sampling in controller mode.

Table 18-16 CLKCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-16DSAMPLER/W0hDelayed sampling. In controller mode the data on the input pin will be delayed sampled by the defined clock cycles. DSAMPLE values can range from 0 to SCR+1. Typically, values of 1 or 2 would suffice.
15-10RESERVEDR0hReserved
9-0SCRR/W0hSerial clock divider. This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate: (SPI functional clock frequency)/((SCR+1)*2). SCR value can be from 0 to 1023.

18.6.14 IFLS Register (Offset = 110h) [Reset = 00000202h]

IFLS is shown in Table 18-17.

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Interrupt FIFO level select register. This register can be used to define the levels at which the TX, RX flags are triggered. The interrupts are generated based on FIFO level. Out of reset, the TXSEL and RXSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark.

Table 18-17 IFLS Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10-8RXSELR/W2hReceive FIFO Level Select. The trigger points for the receive interrupt are as follows:
  • 0h = Reserved
  • 1h = RX FIFO >= 1/4 full
  • 2h = RX FIFO >= 1/2 full (default)
  • 3h = RX FIFO >= 3/4 full
  • 4h = Reserved
  • 5h = RX FIFO is full
  • 6h = Reserved
  • 7h = Trigger when RX FIFO contains >= 1 byte
7-3RESERVEDR0hReserved
2-0TXSELR/W2hTransmit FIFO Level Select. The trigger points for the transmit interrupt are as follows:
  • 0h = Reserved
  • 1h = TX FIFO <= 3/4 empty
  • 2h = TX FIFO <= 1/2 empty (default)
  • 3h = TX FIFO <= 1/4 empty
  • 4h = Reserved
  • 5h = TX FIFO is empty
  • 6h = Reserved
  • 7h = Trigger when TX FIFO has >= 1 byte free

18.6.15 DMACR Register (Offset = 114h) [Reset = 00000000h]

DMACR is shown in Table 18-18.

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DMA Control Register

Table 18-18 DMACR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8TXENR/W0hTransmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.
  • 0h = DIS : Disable TX DMA
  • 1h = EN : Enable TX DMA
7-1RESERVEDR0hReserved
0RXENR/W0hReceive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.
  • 0h = DIS : Disable RX DMA
  • 1h = EN : Enable RX DMA

18.6.16 RXCRC Register (Offset = 118h) [Reset = 00000000h]

RXCRC is shown in Table 18-19.

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Receive CRC register. Reading this register provides the computed CRC value from the receive side CRC unit. Reading this register or writing to this register with any value auto initializes the seed. The seed value is 0xFF when CRCPOLY = 0 and 0xFFFF when CRCPOLY = 1 for CCITT CRC polynomials. Bits[15:8] are a don't care when CRCPOLY = 0.

Table 18-19 RXCRC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR/W0hCRC value

18.6.17 TXCRC Register (Offset = 11Ch) [Reset = 00000000h]

TXCRC is shown in Table 18-20.

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Transmit CRC register. Reading this register provides the computed CRC value from the transmit side CRC unit. Reading this register or writing to this register with any value auto initializes the seed. The seed value is 0xFF when CRCPOLY = 0 and 0xFFFF when CRCPOLY = 1 for CCITT CRC polynomials. Bits[15:8] are a don't care when CRCPOLY = 0.

Table 18-20 TXCRC Register Field Descriptions
BitFieldTypeResetDescription
31AUTOCRCINSRC0hStatus to indicate if Auto CRC has been inserted into TXFIFO. This is applicable only if CTL0.AUTOCRC enable bit is set
  • 0h (R) = NOTINS : Auto CRC not yet inserted
  • 1h (R) = INS : Auto CRC inserted
30-16RESERVEDR0hReserved
15-0DATAR/W0hCRC value

18.6.18 TXFHDR32 Register (Offset = 120h) [Reset = 00000000h]

TXFHDR32 is shown in Table 18-21.

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Header update reigster for 32 bits of header data.

Table 18-21 TXFHDR32 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hThis field can be used to write four bytes of header data

18.6.19 TXFHDR24 Register (Offset = 124h) [Reset = 00000000h]

TXFHDR24 is shown in Table 18-22.

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Header update reigster for 24 bits of header data.

Table 18-22 TXFHDR24 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hThis field can be used to write three bytes of header data

18.6.20 TXFHDR16 Register (Offset = 128h) [Reset = 00000000h]

TXFHDR16 is shown in Table 18-23.

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Header update reigster for 16 bits of data.

Table 18-23 TXFHDR16 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hThis field can be used to write two bytes of header data

18.6.21 TXFHDR8 Register (Offset = 12Ch) [Reset = 00000000h]

TXFHDR8 is shown in Table 18-24.

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Header update reigster for 8 bits of header data.

Table 18-24 TXFHDR8 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hThis field can be used to write one byte of header data

18.6.22 TXFHDRC Register (Offset = 130h) [Reset = 00000000h]

TXFHDRC is shown in Table 18-25.

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Atomic Header control register

Table 18-25 TXFHDRC Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3CSGATER/W0hChip Select Gating control register. If this bit is set header update register writes are blocked when chip select (CS) is active low, and [HDRIGN] bit is set. This bit resets to 0.
  • 0h = UNBLK : The first header update register write is not blocked based on CS active status (low). If no header update occurred when CS was high (inactive), the first header update is allowed when CS is low (active), and the HDRCMT bit is set. The use case is for the external controller to ensure that the SCLK is not driven during this header update. If the header is already updated when CS is high and inactive, HDRCMT is set immediately when CS drops to active low state, and header writes when CS is low are ignored even if this UNBLK bit is set.
  • 1h = BLK : Header update register writes are blocked when CS is active (low)
2HDRCMTR/W0hHeader Committed field. This bit is set when the [HDREN] bit is set and CS is sampled low. This bit remains 0 otherwise. When set, this bit can be written to a value of 0 to clear.
  • 0h = Header update is not committed
  • 1h = Header update is committed
1HDRIGNR/W0hHeader Ignored field. When [CSGATE] is set to BLK, this bit is set when the last Header update register [TXFHDRn.*] is written when CS is low or [HDRCMT] is already set. When [CSGATE] is set to UNBLK, this bit is set only when the header update register is written when [HDRCMT] is already set. This bit remains 0 otherwise. When set, this bit can be written to a value of 0 to clear.
  • 1h = CLEAR : Header update is not ignored
0HDRENR/W0hHeader enable field. When [CSGATE] is set to BLK, this bit has to be set by software to enable this feature. When [CSGATE] is set to UNBLK, this field is set automatically whenever a write to header update registers occurs [TXFHDRn.*]
  • 0h = DIS : Atomic header update feature disable
  • 1h = EN : Atomic header update feature enable

18.6.23 RXDATA Register (Offset = 140h) [Reset = 00000000h]

RXDATA is shown in Table 18-26.

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RXDATA Register. Reading this register returns first value in the RX FIFO. If the FIFO is empty the last read value is returned. Writing has no effect and is ignored.

Table 18-26 RXDATA Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR0hReceived Data. When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer is accessed. As data values are read by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current RX FIFO write pointer. Received data less than 16 bits is automatically right-justified in the receive buffer.

18.6.24 TXDATA Register (Offset = 150h) [Reset = 00000000h]

TXDATA is shown in Table 18-27.

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TXDATA Register. Writing a value in this register puts the data into the TX FIFO. Reading this register returns the last written value.

Table 18-27 TXDATA Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR/W0hTransmit Data. When read, the last entry in the transmit FIFO, pointed to by the current FIFO write pointer is accessed. When written, the entry in the TX FIFO pointed to by the write pointer, is written to. Data values are read from the transmit FIFO by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits.

18.6.25 STA Register (Offset = 160h) [Reset = 00000000h]

STA is shown in Table 18-28.

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Status Register

Table 18-28 STA Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13-8TXFIFOLVLR0hIndicates how many locations of TXFIFO are currently filled with data
7RESERVEDR0hReserved
6TXDONER/W0hTransmit done. Indicates whether the last bit left the Shift register after a transmission
  • 0h (R/W) = TX_ONGOING : Last bit has not yet left the Shift register, and the transmission is ongoing.
  • 1h (R/W) = TX_DONE : Last bit has been shifted out, and the transmission is done
5CSDR/W0hDetection of CS deassertion in the middle of a word transmission results in this error being set. This feature is only available in the peripheral mode.
  • 0h (R/W) = NOERR : No CS posedge is detected before the entire word has been transmitted.
  • 1h (R/W) = ERR : An error is generated when CS posedge (deassertion) is detected before the entire word is transmitted.
4BUSYR0hSPI Busy status
  • 0h = SPI is in idle mode.
  • 1h = SPI is currently transmitting and/or receiving data, or transmit FIFO is not empty.
3RNFR1hReceive FIFO not full status.
  • 0h = Receive FIFO is full.
  • 1h = Receive FIFO is not full.
2RFER1hReceive FIFO empty status.
  • 0h = Receive FIFO is not empty.
  • 1h = Receive FIFO is empty.
1TNFR1hTransmit FIFO not full status.
  • 0h = Transmit FIFO is full.
  • 1h = Transmit FIFO is not full.
0TFER1hTransmit FIFO empty status.
  • 0h = Transmit FIFO is not empty.
  • 1h = Transmit FIFO is empty.

18.6.26 CLKCFG Register (Offset = 1000h) [Reset = 00000000h]

CLKCFG is shown in Table 18-29.

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Clock Enable Register

Table 18-29 CLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ENABLER/W0hSPI main clock Enable