SWRU626 December   2025 CC3501E , CC3551E

 

  1.   1
  2. 1 Read This First
    1. 1.1 About This Manual
    2. 1.2 Register, Field, and Bit Calls
    3.     Trademarks
  3. 2 Architecture Overview
    1. 2.1  Target Applications
    2. 2.2  Introduction
    3. 2.3  Internal System Diagram
    4. 2.4  Arm Cortex M33
      1. 2.4.1 Processor Core
      2. 2.4.2 SysTick Timer
      3. 2.4.3 Nested Vectored Interrupt Controller
      4. 2.4.4 System Control Block (SCB)
      5. 2.4.5 TI AI instruction extensions
    5. 2.5  Power Management
      1. 2.5.1 VDD_MAIN
      2. 2.5.2 VDD_IO
      3. 2.5.3 VDDSF
      4. 2.5.4 VDD_PA
    6. 2.6  Debug Subsystem (DEBUGSS)
    7. 2.7  Memory Subsystem (MEMSS)
      1. 2.7.1 External Memory Interface
    8. 2.8  Hardware Security Module
    9. 2.9  General Purpose Timers (GPT)
    10. 2.10 Real Time Clock (RTC)
    11. 2.11 Direct Memory Access
    12. 2.12 GPIOs
    13. 2.13 Communication Peripherals
      1. 2.13.1 UART
      2. 2.13.2 I2C
      3. 2.13.3 SPI
      4. 2.13.4 I2S
      5. 2.13.5 SDMMC
      6. 2.13.6 SDIO
      7. 2.13.7 CAN
      8. 2.13.8 ADC
  4. 3  Arm Cortex-M33 Processor
    1. 3.1 Arm Cortex-M33 Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 M33 instantiation parameters
    4. 3.4 Arm Cortex-M33 System Peripheral Details
      1. 3.4.1 Floating Point Unit (FPU)
      2. 3.4.2 Memory Protection Unit (MPU)
      3. 3.4.3 Digital Signal Processing (DSP)
      4. 3.4.4 Security Attribution Unit (SAU)
      5. 3.4.5 System Timer
      6. 3.4.6 Nested Vectored Interrupt Controller
      7. 3.4.7 System Control Block
      8. 3.4.8 System Control Space
    5. 3.5 CPU Sub-System Peripheral Details
      1. 3.5.1 Trace Port Interface Unit (TPIU)
      2. 3.5.2 DAP Bridge and Debug Authentication
      3. 3.5.3 Implementation Defined Attribution Unit (IDAU)
    6. 3.6 Programming Model
      1. 3.6.1 Modes of operation and execution
        1. 3.6.1.1 Security states
        2. 3.6.1.2 Operating modes
        3. 3.6.1.3 Operating states
        4. 3.6.1.4 Privileged access and unprivileged user access
      2. 3.6.2 Instruction set summary
      3. 3.6.3 Memory model
        1. 3.6.3.1 Private Peripheral Bus
        2. 3.6.3.2 Unaligned accesses
      4. 3.6.4 Processor core registers summary
      5. 3.6.5 Exceptions
        1. 3.6.5.1 Exception handling and prioritization
    7. 3.7 TrustZone-M
      1. 3.7.1 Overview
      2. 3.7.2 M33 Configuration
      3. 3.7.3 Description of elements
        1. 3.7.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 3.7.3.1.1 Expected use
    8. 3.8 CC35xx Host MCU Registers
      1. 3.8.1 HOSTMCU_AON Registers
      2. 3.8.2 HOST_MCU Registers
      3. 3.8.3 HOST_MCU_SEC Registers
    9. 3.9 Arm® Cortex®-M33 Registers
      1. 3.9.1  CPU_ROM_TABLE Registers
      2. 3.9.2  TPIU Registers
      3. 3.9.3  DCB Registers
      4. 3.9.4  DIB Registers
      5. 3.9.5  DWT Registers
      6. 3.9.6  FPB Registers
      7. 3.9.7  FPE Registers
      8. 3.9.8  ICB Registers
      9. 3.9.9  ITM Registers
      10. 3.9.10 MPU Registers
      11. 3.9.11 NVIC Registers
      12. 3.9.12 SAU Registers
      13. 3.9.13 SCB Registers
      14. 3.9.14 SYSTIMER Registers
      15. 3.9.15 SYSTICK Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation to HardFault
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Manager
      1. 5.4.1 Introduction
      2. 5.4.2 Interrupts List
      3. 5.4.3 Wakeup Sources
      4. 5.4.4 Shared Peripherals MUX Selector
        1. 5.4.4.1 ADC HW Event Selector Mux
        2. 5.4.4.2 I2S HW Event Selector Mux
        3. 5.4.4.3 PDM HW Event Selector Mux
      5. 5.4.5 Timers MUX Selector Mux
        1. 5.4.5.1 SysTimer0 HW Event Selector Mux
        2. 5.4.5.2 SysTimer1 HW Event Selector Mux
        3. 5.4.5.3 RTC HW Event Selector Mux
      6. 5.4.6 GPTIMERs MUX Selector Mux
        1. 5.4.6.1 GPTIMER0 HW Event Selector Mux
        2. 5.4.6.2 GPTIMER1 HW Event Selector Mux
    5. 5.5 SOC_IC Registers
    6. 5.6 SOC_AON Registers
    7. 5.7 SOC_AAON Registers
  7. 6 Debug Subsystem (DEBUGSS)
    1. 6.1 Introduction
    2. 6.2 Block Diagram
    3. 6.3 Overview
    4. 6.4 Physical Interface
    5. 6.5 Debug Access Ports
    6. 6.6 Debug Features
      1. 6.6.1 Processor Debug
      2. 6.6.2 Breakpoint Unit (BPU)
      3. 6.6.3 Peripheral Debug
    7. 6.7 Behavior in Low Power Modes
    8. 6.8 Debug Access Control
    9. 6.9 SOC_DEBUGSS Registers
  8. 7 Power, Reset, Clock Management
    1. 7.1 Power Management
      1. 7.1.1 Power Supply System
        1. 7.1.1.1 VDD_MAIN
        2. 7.1.1.2 VIO
        3. 7.1.1.3 VDDSF
        4. 7.1.1.4 VPA
      2. 7.1.2 Power States
      3. 7.1.3 Power Domains
      4. 7.1.4 Brownout (BOR)
      5. 7.1.5 Boot Sequence
    2. 7.2 Reset
      1. 7.2.1 Reset Cause
      2. 7.2.2 Watchdog Timer (WDT)
    3. 7.3 Clocks
      1. 7.3.1 Fast Clock
      2. 7.3.2 Slow Clock
        1. 7.3.2.1 Slow Clock Overview
        2. 7.3.2.2 Slow Clock Tree
        3. 7.3.2.3 Slow Clock Boot Process
    4. 7.4 PRCM_AON Registers
    5. 7.5 PRCM_SCRATCHPAD Registers
  9. 8 Memory Subsystem (MEMSS)
    1. 8.1  Introduction
    2. 8.2  SRAM
    3. 8.3  D-Cache
    4. 8.4  Flash
    5. 8.5  PSRAM
    6. 8.6  XiP Memory Access
      1. 8.6.1 OTFDE
      2. 8.6.2 xSPI
      3. 8.6.3 Topology
      4. 8.6.4 µDMA
      5. 8.6.5 Arbiter
    7. 8.7  ICACHE Registers
    8. 8.8  DCACHE Registers
    9. 8.9  OSPI Registers
    10. 8.10 HOST_XIP Registers
  10. 9 Hardware Security Module (HSM)
    1. 9.1 Introduction
    2. 9.2 Overview
    3. 9.3 Mailbox and Register Access Firewall
    4. 9.4 DMA Firewall
    5. 9.5 HSM Key Storage
    6. 9.6 HSM Registers
    7. 9.7 HSM_NON_SEC Registers
    8. 9.8 HSM_SEC Registers
  11. 10Device Boot and Bootloader
    1. 10.1 CC35xx Boot Concept
    2. 10.2 Features
    3. 10.3 Vendor Images Format and Processing
      1. 10.3.1 External Flash Arrangement
      2. 10.3.2 Vendor Images Format
    4. 10.4 Boot Flows
      1. 10.4.1 Application Execution Boot Flow
      2. 10.4.2 Activation Flow
      3. 10.4.3 Initial Programming Flow
      4. 10.4.4 Reprogramming Flow
      5. 10.4.5 Wireless Connectivity Testing Tool Flow
    5. 10.5 Chain of Trust
  12. 11Direct Memory Access (DMA)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Channels Assignment
      2. 11.3.2 Transfer Types
      3. 11.3.3 Addressing Modes
      4. 11.3.4 Transfer Modes
      5. 11.3.5 DMA Aligner Support
      6. 11.3.6 Initiating DMA Transfers
      7. 11.3.7 Stopping DMA Transfers
      8. 11.3.8 Channel Priorities
      9. 11.3.9 DMA Interrupts
    4. 11.4 HOST_DMA Registers
  13. 12One Time Programming (OTP)
  14. 13General Purpose Timers (GPT)
    1. 13.1 Overview
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1  Prescaler
      2. 13.3.2  Counter
      3. 13.3.3  Target
      4. 13.3.4  Channel Input Logic
      5. 13.3.5  Channel Output Logic
      6. 13.3.6  Channel Actions
        1. 13.3.6.1 Period and Pulse Width Measurement
        2. 13.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 13.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 13.3.7  Channel Capture Configuration
      8. 13.3.8  Channel Filters
        1. 13.3.8.1 Setting up the Channel Filters
      9. 13.3.9  Synchronize Multiple GPTimers
      10. 13.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 13.4 Timer Modes
      1. 13.4.1 Quadrature Decoder
      2. 13.4.2 DMA
      3. 13.4.3 IR Generation
      4. 13.4.4 Fault and Park
      5. 13.4.5 Dead-Band
      6. 13.4.6 Dead-Band, Fault and Park
      7. 13.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 13.5 GPTIMER Registers
  15. 14System Timer (SysTimer)
    1. 14.1 Overview
    2. 14.2 Block Diagram
    3. 14.3 Functional Description
      1. 14.3.1 Common Channel Features
        1. 14.3.1.1 Compare Mode
        2. 14.3.1.2 Capture Mode
        3. 14.3.1.3 Additional Channel Arming Methods
      2. 14.3.2 Interrupts and Events
    4. 14.4 SYSRESOURCES Registers
    5. 14.5 SYSTIM Registers
  16. 15Real-Time Clock (RTC)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Interrupts and Events
      1. 15.3.1 Input Event
      2. 15.3.2 Output Event
      3. 15.3.3 Arming and Disarming Channels
    4. 15.4 CAPTURE and COMPARE Configurations
      1. 15.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 15.4.2 CHANNEL 1 - CAPTURE CHANNEL
    5. 15.5 RTC Registers
  17. 16General Purpose Input/Output (GPIOs)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 I/O Mapping and Configuration
      1. 16.3.1 Basic I/O Mapping
      2. 16.3.2 Pin Mapping
    4. 16.4 Edge Detection
    5. 16.5 GPIO
    6. 16.6 I/O Pins
    7. 16.7 Unused Pins
    8. 16.8 IOMUX Registers
  18. 17Universal Asynchronous Receivers/Transmitters (UART)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 UART Functional Description
      1. 17.3.1 Transmit and Receive Logic
      2. 17.3.2 Baud Rate Generation
      3. 17.3.3 FIFO Operation
        1. 17.3.3.1 FIFO Remapping
      4. 17.3.4 Data Transmission
      5. 17.3.5 Flow Control
      6. 17.3.6 IrDA Encoding and Decoding
      7. 17.3.7 Interrupts
      8. 17.3.8 Loopback Operation
    4. 17.4 UART-LIN Specification
      1. 17.4.1 Break transmission in UART mode
      2. 17.4.2 Break reception in UART mode
      3. 17.4.3 Break/Synch transmission in LIN mode
      4. 17.4.4 Break/Synch reception in LIN mode
      5. 17.4.5 Dormant mode operation
      6. 17.4.6 Event signal generation
      7. 17.4.7 Event signal detection when device is in active/idle modes
      8. 17.4.8 Event signal detection when device is in sleep mode
    5. 17.5 Interface to Host DMA
    6. 17.6 Initialization and Configuration
    7. 17.7 UART Registers
  19. 18Serial Peripheral Interface (SPI)
    1. 18.1 Overview
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Signal Description
    3. 18.3 Functional Description
      1. 18.3.1  Clock Control
      2. 18.3.2  FIFO Operation
        1. 18.3.2.1 Transmit FIFO
        2. 18.3.2.2 Repeated Transmit Operation
        3. 18.3.2.3 Receive FIFO
        4. 18.3.2.4 FIFO Flush
      3. 18.3.3  Interrupts
      4. 18.3.4  Data Format
      5. 18.3.5  Delayed Data Sampling
      6. 18.3.6  Chip Select Control
      7. 18.3.7  Command Data Control
      8. 18.3.8  Protocol Descriptions
        1. 18.3.8.1 Motorola SPI Frame Format
        2. 18.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 18.3.8.3 MICROWIRE Frame Format
      9. 18.3.9  CRC Configuration
      10. 18.3.10 Auto CRC Functionality
      11. 18.3.11 SPI Status
      12. 18.3.12 Debug Halt
    4. 18.4 Host DMA Operation
    5. 18.5 Initialization and Configuration
    6. 18.6 SPI Registers
  20. 19Inter-Integrated Circuit (I2C) Interface
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Clock Control
        1. 19.3.1.1 Internal Clock
        2. 19.3.1.2 External Clock
      2. 19.3.2 General Architecture
        1. 19.3.2.1  Start and Stop Conditions
        2. 19.3.2.2  Data Format with 7-Bit Address
        3. 19.3.2.3  Data Format with 10-Bit Addressing
          1. 19.3.2.3.1 Additional 10-Bit Scenarios
        4. 19.3.2.4  Acknowledge
        5. 19.3.2.5  Repeated Start
        6. 19.3.2.6  Clock Stretching
        7. 19.3.2.7  Arbitration
        8. 19.3.2.8  Multi-Controller mode
        9. 19.3.2.9  Glitch Suppression
        10. 19.3.2.10 FIFO Operation
        11. 19.3.2.11 Burst Mode Operation
        12. 19.3.2.12 DMA Operation
        13. 19.3.2.13 Flush Stale Tx Data in Target Mode
          1. 19.3.2.13.1 Recommended Sequence
        14. 19.3.2.14 SMBUS 3.0 Support
          1. 19.3.2.14.1 Quick Command
          2. 19.3.2.14.2 Acknowledge Control
          3. 19.3.2.14.3 Alert Response protocol
          4. 19.3.2.14.4 Address Resolution Protocol
          5. 19.3.2.14.5 Enhanced Acknowledge Control
    4. 19.4 Initialization and Configuration
    5. 19.5 Interrupts
    6. 19.6 I2C Registers
  21. 20Secure Digital Multimedia Card (SDMMC)
    1. 20.1 Introduction
      1. 20.1.1 SDMMC Features
      2. 20.1.2 Integration
    2. 20.2 Functional Description
      1. 20.2.1  SDMMC Functional Modes
        1. 20.2.1.1 SDMMC Connected to an SD Card
        2. 20.2.1.2 Protocol and Data Format
          1. 20.2.1.2.1 Protocol
          2. 20.2.1.2.2 Data Format
      2. 20.2.2  SD Card Feedback
      3. 20.2.3  Resets
        1. 20.2.3.1 Hardware Reset
        2. 20.2.3.2 Software Reset
      4. 20.2.4  Interrupt Requests
        1. 20.2.4.1 Interrupt-Driven Operation
        2. 20.2.4.2 Polling
      5. 20.2.5  DMA Modes
        1. 20.2.5.1 DMA Peripheral Mode Operations
          1. 20.2.5.1.1 DMA Receive Mode
          2. 20.2.5.1.2 DMA Transmit Mode
      6. 20.2.6  Buffer Management
        1. 20.2.6.1 Data Buffer
          1. 20.2.6.1.1 Memory Size and Block Length
          2. 20.2.6.1.2 Data Buffer Status
      7. 20.2.7  Transfer Process
        1. 20.2.7.1 Different Types of Commands
        2. 20.2.7.2 Different Types of Responses
      8. 20.2.8  Transfer or Command Status and Error Reporting
        1. 20.2.8.1 Busy Timeout for R1b, R5b Response Type
        2. 20.2.8.2 Busy Timeout After Write CRC Status
        3. 20.2.8.3 Write CRC Status Timeout
        4. 20.2.8.4 Read Data Timeout
      9. 20.2.9  Auto Command 12 Timings
        1. 20.2.9.1 Auto Command 12 Timings During Write Transfer
        2. 20.2.9.2 Auto Command 12 Timings During Read Transfer
      10. 20.2.10 Transfer Stop
      11. 20.2.11 Output Signals Generation
        1. 20.2.11.1 Generation on Falling Edge of SDMMC Clock
        2. 20.2.11.2 Generation on Rising Edge of SDMMC Clock
      12. 20.2.12 Test Registers
      13. 20.2.13 SDMMC Hardware Status Features
    3. 20.3 Low-Level Programming Models
      1. 20.3.1 SDMMC Initialization Flow
        1. 20.3.1.1 Enable OCP and CLKADPI Clocks
        2. 20.3.1.2 SD Soft Reset Flow
        3. 20.3.1.3 Set SD Default Capabilities
        4. 20.3.1.4 SDMMC Host and Bus Configuration
      2. 20.3.2 Operational Modes Configuration
        1. 20.3.2.1 Basic Operations for SDMMC
        2. 20.3.2.2 Card Detection, Identification, and Selection
    4. 20.4 SDMMC Registers
  22. 21Secure Digital Input/Output (SDIO)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 SDIO Interface Description
      2. 21.3.2 Protocol and Data Format
      3. 21.3.3 I/O Read/Write Command
        1. 21.3.3.1 IO_WR_DIRECT Command (CMD52)
        2. 21.3.3.2 IO_WR_EXTENDED Command (CMD53)
      4. 21.3.4 Reset
      5. 21.3.5 FIFO Operation
        1. 21.3.5.1 Rx FIFO (For Host Write)
        2. 21.3.5.2 Tx FIFO (For Host Read)
      6. 21.3.6 Interrupt Request
        1. 21.3.6.1 External Host IRQ
        2. 21.3.6.2 M33 IRQ
      7. 21.3.7 Transaction Details
        1. 21.3.7.1 Host write to SDIO IP (Rx FIFO)
          1. 21.3.7.1.1 Host write to SDIO IP (Rx FIFO) – Long SW latency case
          2. 21.3.7.1.2 Host write to SDIO IP (Rx FIFO) – CRC Error Case
        2. 21.3.7.2 Host reads from SDIO (TX buffer)
    4. 21.4 SDIO_CORE Registers
    5. 21.5 SDIO_CARD_FN1 Registers
  23. 22Inter-Integrated Circuit Sound (I2S)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  Signal Descriptions
    4. 22.4  Functional Description
      1. 22.4.1 Pin Configuration
      2. 22.4.2 Serial Format Configuration
        1. 22.4.2.1 Register Configuration
      3. 22.4.3 Left-Justified (LJF)
        1. 22.4.3.1 Register Configuration
      4. 22.4.4 Right-Justified (RJF)
        1. 22.4.4.1 Register Configuration
      5. 22.4.5 DSP
        1. 22.4.5.1 Register Configuration
      6. 22.4.6 Clock Configuration
    5. 22.5  Memory Interface
      1. 22.5.1 Sample Word Length
      2. 22.5.2 Padding Mechanism
      3. 22.5.3 Channel Mapping
      4. 22.5.4 Sample Storage in Memory
      5. 22.5.5 DMA Operation
        1. 22.5.5.1 Start-Up
        2. 22.5.5.2 Operation
        3. 22.5.5.3 Shutdown
    6. 22.6  Samplestamp Generator
      1. 22.6.1 Samplestamp Counters
      2. 22.6.2 Start-Up Triggers
      3. 22.6.3 Samplestamp Capture
      4. 22.6.4 Achieving constant audio latency
    7. 22.7  Error Detection
    8. 22.8  Usage
      1. 22.8.1 Start-Up Sequence
      2. 22.8.2 Shutdown Sequence
    9. 22.9  I2S Configuration Guideline
    10. 22.10 I2S Registers
  24. 23Pulse Density Modulation (PDM)
    1. 23.1  Introduction
    2. 23.2  Block Diagram
    3. 23.3  Input Selection
      1. 23.3.1 PDM Data Mode
      2. 23.3.2 Manchester Input Mode
    4. 23.4  CIC Filter
      1. 23.4.1 Filter Design
      2. 23.4.2 Digital Filter Output
      3. 23.4.3 Offset Binary Mode
      4. 23.4.4 Twos-Complement Mode
    5. 23.5  FIFO Organization in Different Modes
      1. 23.5.1 Single Mono Microphone Configuration
        1. 23.5.1.1 24-bit Sample Size
          1. 23.5.1.1.1 32-bit Data Read
        2. 23.5.1.2 16-bit Sample Size
          1. 23.5.1.2.1 32-bit Data Read
          2. 23.5.1.2.2 16-bit Data Read
        3. 23.5.1.3 8-bit Sample Size
          1. 23.5.1.3.1 32-bit Data Read
          2. 23.5.1.3.2 16-bit Data Read
          3. 23.5.1.3.3 8-bit Data Read
      2. 23.5.2 Stereo or Dual Mono Microphone Configuration
        1. 23.5.2.1 24-bit Sample Size
          1. 23.5.2.1.1 32-bit Data Read
        2. 23.5.2.2 16-bit Sample Size
          1. 23.5.2.2.1 32-bit Data Read
          2. 23.5.2.2.2 16-bit Data Read
        3. 23.5.2.3 8-bit Sample Size
          1. 23.5.2.3.1 32-bit Data Read
          2. 23.5.2.3.2 16-bit Data Read
          3. 23.5.2.3.3 8-bit Data Read
      3. 23.5.3 FIFO Threshold Setting
      4. 23.5.4 Reset FIFO
    6. 23.6  Automatic Gain Control (AGC)
      1. 23.6.1 Operation in 2's Complement Format
      2. 23.6.2 Operation in Offset Binary Format
    7. 23.7  Interrupts
    8. 23.8  Clock Select and Control
    9. 23.9  DMA Operation
    10. 23.10 Samplestamp Generator
      1. 23.10.1 Samplestamp Counters
      2. 23.10.2 Start-Up Triggers
      3. 23.10.3 Samplestamp Capture
      4. 23.10.4 Achieving Constant Audio Latency
    11. 23.11 Debug‑Mode Flag Behavior
    12. 23.12 Software Guidelines
    13. 23.13 PDM Registers
  25. 24Analog to Digital Converter (ADC)
    1. 24.1 Overview
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1  ADC Core
      2. 24.3.2  Voltage Reference Options
      3. 24.3.3  Internal Channels
      4. 24.3.4  Resolution Modes
      5. 24.3.5  ADC Clocking
      6. 24.3.6  Power Down Behavior
      7. 24.3.7  Sampling Trigger Sources and Sampling Modes
        1. 24.3.7.1 AUTO Sampling Mode
        2. 24.3.7.2 MANUAL Sampling Mode
      8. 24.3.8  Sampling Period
      9. 24.3.9  Conversion Modes
      10. 24.3.10 ADC Data Format
      11. 24.3.11 Status Register
      12. 24.3.12 ADC Events
        1. 24.3.12.1 Generic Event Publishers (INT_EVENT0 & INT_EVENT1)
        2. 24.3.12.2 DMA Trigger Event Publisher (INT_EVENT2)
        3. 24.3.12.3 Generic Event Subscriber
      13. 24.3.13 Advanced Features
        1. 24.3.13.1 Window Comparator
        2. 24.3.13.2 DMA & FIFO Operation
          1. 24.3.13.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
          2. 24.3.13.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
          3. 24.3.13.2.3 DMA/CPU Operation Summary Matrix
        3. 24.3.13.3 Ad-hoc Single Conversion
    4. 24.4 ADC Registers
  26. 25Controller Area Network (CAN)
    1. 25.1 Introduction
    2. 25.2 Functions
    3. 25.3 DCAN Subsystem
    4. 25.4 DCAN Functional Description
      1. 25.4.1 Operating Modes
        1. 25.4.1.1 Software Initialization
        2. 25.4.1.2 Normal Operation
        3. 25.4.1.3 Restricted Operation Mode
        4. 25.4.1.4 Bus Monitoring Mode
        5. 25.4.1.5 Disabled Automatic Retransmission
          1. 25.4.1.5.1 Frame Transmission in DAR Mode
        6. 25.4.1.6 Power Down (Sleep Mode)
          1. 25.4.1.6.1 DCAN clock stop and wake operations
          2. 25.4.1.6.2 DCAN debug suspend operation
        7. 25.4.1.7 Test Modes
          1. 25.4.1.7.1 External Loop Back Mode
          2. 25.4.1.7.2 Internal Loop Back Mode
      2. 25.4.2 Timestamp Generation
        1. 25.4.2.1 Block Diagram
      3. 25.4.3 Timeout Counter
      4. 25.4.4 Rx Handling
        1. 25.4.4.1 Acceptance Filtering
          1. 25.4.4.1.1 Range Filter
          2. 25.4.4.1.2 Filter for specific IDs
          3. 25.4.4.1.3 Classic Bit Mask Filter
          4. 25.4.4.1.4 Standard Message ID Filtering
          5. 25.4.4.1.5 Extended Message ID Filtering
        2. 25.4.4.2 Rx FIFOs
          1. 25.4.4.2.1 Rx FIFO Blocking Mode
          2. 25.4.4.2.2 Rx FIFO Overwrite Mode
        3. 25.4.4.3 Dedicated Rx Buffers
          1. 25.4.4.3.1 Rx Buffer Handling
        4. 25.4.4.4 Debug on CAN Support
          1. 25.4.4.4.1 Filtering for Debug Messages
          2. 25.4.4.4.2 Debug Message Handling
      5. 25.4.5 Tx Handling
        1. 25.4.5.1 Transmit Pause
        2. 25.4.5.2 Dedicated Tx Buffers
        3. 25.4.5.3 Tx FIFO
        4. 25.4.5.4 Tx Queue
        5. 25.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 25.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 25.4.5.7 Transmit Cancellation
        8. 25.4.5.8 Tx Event Handling
      6. 25.4.6 FIFO Acknowledge Handling
      7. 25.4.7 DCAN Message RAM
        1. 25.4.7.1 Message RAM Configuration
        2. 25.4.7.2 Rx Buffer and FIFO Element
        3. 25.4.7.3 Tx Buffer Element
        4. 25.4.7.4 Tx Event FIFO Element
        5. 25.4.7.5 Standard Message ID Filter Element
        6. 25.4.7.6 Extended Message ID Filter Element
      8. 25.4.8 Interrupt Requests
    5. 25.5 DCAN Wrapper
    6. 25.6 DCAN Clock Enable
    7. 25.7 DCAN Registers
  27. 26Revision History

25.7 DCAN Registers

Table 25-10 lists the memory-mapped registers for the DCAN registers. All register offset addresses not listed in Table 25-10 should be considered as reserved locations and the register contents should not be modified.

Table 25-10 DCAN Registers
OffsetAcronymRegister NameSection
0hCRELCore ReleaseSection 25.7.1
4hENDNEndianness IdentifierSection 25.7.2
ChDBTPData Bit TimingSection 25.7.3
10hTESTTest ControlSection 25.7.4
14hRWDRAM Watchdog CounterSection 25.7.5
18hCCCRConfiguration Control RegisterSection 25.7.6
1ChNBTPNominal Bit TimingSection 25.7.7
20hTSCCTimestamp Counter ConfigurationSection 25.7.8
24hTSCVTimestamp CounterSection 25.7.9
28hTOCCTimeout Counter ConfigurationSection 25.7.10
2ChTOCVDCAN Timeout Counter ValueSection 25.7.11
40hECRError CounterSection 25.7.12
44hPSRProtocol StatusSection 25.7.13
48hTDCRDCAN Transmitter Delay Compensation RegisterSection 25.7.14
50hIRDCAN Interrupt RegisterSection 25.7.15
54hIEDCAN Interrupt EnableSection 25.7.16
58hILSInterrupt Line SelectionSection 25.7.17
5ChILEInterrupt Line EnableSection 25.7.18
80hGFCGlobal Filter ConfigurationSection 25.7.19
84hSIDFCStandard Filter ConfigurationSection 25.7.20
88hXIDFCExtended Filter ConfigurationSection 25.7.21
90hXIDAMDCAN Extended ID and MaskSection 25.7.22
94hHPMSPriority Message StatusSection 25.7.23
98hNDAT1New Data RegisterSection 25.7.24
9ChNDAT2DCAN New Data 2Section 25.7.25
A0hRXF0CReceive FIFO ConfigurationSection 25.7.26
A4hRXF0SReceive FIFO StatusSection 25.7.27
A8hRXF0AReceive FIFO AcknowledgeSection 25.7.28
AChRXBCReceive Buffer ConfigurationSection 25.7.29
B0hRXF1CReceive Buffer ConfigurationSection 25.7.30
B4hRXF1SReceive FIFO StatusSection 25.7.31
B8hRXF1AReceive FIFO AcknowledgeSection 25.7.32
BChRXESCReceive Element SizeSection 25.7.33
C0hTXBCTransmit Buffer ConfigurationSection 25.7.34
C4hTXFQSTransmit Queue StatusSection 25.7.35
C8hTXESCTransmit Element SizeSection 25.7.36
CChTXBRPAPTransmit Request StatusSection 25.7.37
D0hTXBARDCAN Tx Buffer Add RequestSection 25.7.38
D4hTXBCRDCAN Tx Buffer Cancellation RequestSection 25.7.39
D8hTXBTOTransmission StatusSection 25.7.40
DChTXBCFTransmission Cancellation StatusSection 25.7.41
E0hTXTIEDCAN Tx Buffer Transmission Interrupt EnableSection 25.7.42
E4hTXBCIETransmission Cancellation InterruptSection 25.7.43
F0hTXEFCTransmit Event ConfigurationSection 25.7.44
F4hTXEFSDCAN Tx Event FIFO StatusSection 25.7.45
F8hTXEFATransmit Event AcknowledgementSection 25.7.46
200hSSPIDSubsystem RevisionSection 25.7.47
204hSSCTLSubsystem ControlSection 25.7.48
208hSSSTASubsystem StatusSection 25.7.49
20ChSSICSDCAN Subsystem Interrupt Clear Shadow RegisterSection 25.7.50
210hSSIRSInterrupt Raw StatusSection 25.7.51
214hSSIECSInterrupt Disable RegisterSection 25.7.52
218hSSIEDCAN Subsystem Interrupt Enable RegisterSection 25.7.53
21ChSSIESMasked Interrupt StatusSection 25.7.54
220hSSEOIInterrupt CompletionSection 25.7.55
224hEXTTSPSTimestamp PrescalerSection 25.7.56
228hEXTTSUSITimestamp Interrupt CounterSection 25.7.57
400hERRREVRevision IdentifierSection 25.7.58
408hERRVECError Controller SelectionSection 25.7.59
40ChERRSTAError StatusSection 25.7.60
410hERRWRAPREVWrapper RevisionSection 25.7.61
414hERRCTLDCAN ECC ControlSection 25.7.62
418hERRCTL1DCAN ECC Error Control 1 RegisterSection 25.7.63
41ChERRCTL2Error Control ConfigurationSection 25.7.64
420hERRSTA1DCAN ECC Error Status 1 RegisterSection 25.7.65
424hERRSTA2Error StatusSection 25.7.66
428hERRSTA3DCAN ECC Error Status 3 RegisterSection 25.7.67
43ChSECEOIError Correction AcknowledgmentSection 25.7.68
440hSECSTAError Correction StatusSection 25.7.69
480hSECENSETError Correction EnableSection 25.7.70
4C0hSECENCLRError Correction EnableSection 25.7.71
53ChDEDEOIDCAN Double Error Detected End of Interrupt RegisterSection 25.7.72
540hDEDSTADCAN Double Error Detected Interrupt Status RegisterSection 25.7.73
580hDEDENSETError Interrupt EnableSection 25.7.74
5C0hDEDENCLRError Detection ClearSection 25.7.75
600hAGGRENSETDCAN error Aggregator Enable Set RegisterSection 25.7.76
604hAGGRENCLRDCAN error Aggregator Enable Clear RegisterSection 25.7.77
608hAGGRSTASETDCAN error Aggregator Status Set RegisterSection 25.7.78
60ChAGGRSTACLRDCAN error Aggregator Status Clear RegisterSection 25.7.79
800hDESCModule IdentificationSection 25.7.80
844hIMASK0Interrupt MaskSection 25.7.81
848hRIS0Interrupt Status FlagsSection 25.7.82
84ChMIS0Masked Interrupt StatusSection 25.7.83
850hISET0Interrupt Set ControlSection 25.7.84
854hICLR0Interrupt ClearSection 25.7.85
868hIMASK1Interrupt Mask ControlSection 25.7.86
86ChRIS1Raw Interrupt StatusSection 25.7.87
870hMIS1Masked Interrupt StatusSection 25.7.88
874hISET1Interrupt Set RegisterSection 25.7.89
878hICLR1Interrupt ClearSection 25.7.90
904hCLKDIVClock DividerSection 25.7.91
908hCLKCTLClock ControlSection 25.7.92
90ChCLKSTAClock StatusSection 25.7.93
924hDMA0CTLDMA ControlSection 25.7.94
92ChDMA1CTLDMA Control RegisterSection 25.7.95
938hTTOFE0Receive Buffer AddressSection 25.7.96
948hTTOFE1Receive Buffer BaseSection 25.7.97
950hTTONDAT1NDAT1 Value RegisterSection 25.7.98
2000hCLKCFGAudio clock selection and DCAN IP enable register.Section 25.7.99

Complex bit access types are encoded to fit into small table cells. Table 25-11 shows the codes that are used for access types in this section.

Table 25-11 DCAN Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
RCR
C		Read
to Clear
RSR
S		Read
to Set
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
W1SQW
1S
Q		Write
1 to set
Qualified. A condition must be met for this operation to occur.
WDW
D		Write
Decrement. Decrements the specified bit field by the amount written.
WIW
I		Write
Increment. Increments the specified bit field by the amount written.
WQW
Q		Write
Qualified. A condition must be met for this operation to occur.
Reset or Default Value
-nValue after reset or the default value

25.7.1 CREL Register (Offset = 0h) [Reset = 32380608h]

CREL is shown in Table 25-12.

Return to the Summary Table.

DCAN Core Release Register

Table 25-12 CREL Register Field Descriptions
BitFieldTypeResetDescription
31-28RELR3hCore Release. One digit, BCD-coded.
27-24STEPR2hStep of Core Release. One digit, BCD-coded.
23-20SUBSTEPR3hSub-Step of Core Release. One digit, BCD-coded.
19-16YEARR8hTime Stamp Year. One digit, BCD-coded.
15-8MONR6hTime Stamp Month. Two digits, BCD-coded.
7-0DAYR8hTime Stamp Day. Two digits, BCD-coded.

25.7.2 ENDN Register (Offset = 4h) [Reset = 87654321h]

ENDN is shown in Table 25-13.

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DCAN Endian Register

Table 25-13 ENDN Register Field Descriptions
BitFieldTypeResetDescription
31-0ETVR87654321hEndianess Test Value. Reading the constant value maintained in this register allows software to determine the endianess of the host CPU.

25.7.3 DBTP Register (Offset = Ch) [Reset = 00000A33h]

DBTP is shown in Table 25-14.

Return to the Summary Table.

This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programmed in the range of 4 to 49 time quanta. The CAN time quantum may be programmed in the range of 1 to 32 m_can_cclk periods. tq = (DBRP + 1) mtq. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) (DTSEG1 + DTSEG2 + 3) tq or (functional values) (Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2) tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.

Table 25-14 DBTP Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23TDCR/WQ0hTransmitter Delay Compensation 0 Transmitter Delay Compensation disabled 1 Transmitter Delay Compensation enabled +I107
22-21RESERVEDR0hReserved
20-16DBRPR/WQ0hData Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-13RESERVEDR0hReserved
12-8DTSEG1R/WQAhData Time Segment Before Sample Point. Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7-4DTSEG2R/WQ3hData Time Segment After Sample Point. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
3-0DSJWR/WQ3hData Resynchronization Jump Width. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

25.7.4 TEST Register (Offset = 10h) [Reset = 000000X0h]

TEST is shown in Table 25-15.

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Write access to the Test Register has to be enabled by setting bit CCCR.TEST to '1'. All Test Register functions are set to their reset values when bit CCCR.TEST is reset. Loop Back Mode and software control of the internal CAN TX pin are hardware test modes. Programming of TX ? "00" may disturb the message transfer on the CAN bus.

Table 25-15 TEST Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7RXRXhReceive Pin. Monitors the actual value of the CAN receive pin. 0 The CAN bus is dominant (CAN RX pin = '0') 1 The CAN bus is recessive (CAN RX pin = '1')
6-5TXR/WQ0hControl of Transmit Pin 00 CAN TX pin controlled by the CAN Core, updated at the end of the CAN bit time 01 Sample Point can be monitored at CAN TX pin 10 Dominant ('0') level at CAN TX pin 11 Recessive ('1') at CAN TX pin Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
4LBCKR/WQ0hLoop Back Mode 0 Reset value, Loop Back Mode is disabled 1 Loop Back Mode is enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
3-0RESERVEDR0hReserved

25.7.5 RWD Register (Offset = 14h) [Reset = 00000000h]

RWD is shown in Table 25-16.

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DCAN RAM Watchdog

Table 25-16 RWD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8WDVR0hWatchdog Value. Actual Message RAM Watchdog Counter Value. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access via the DCAN's Generic Commander Interface starts the Message RAM Watchdog Counter with the value configured by the WDC field. The counter is reloaded with WDC when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to zero, the counter stops and interrupt flag DCAN_IR.WDI is set. The RAM Watchdog Counter is clocked by the host (system) clock.
7-0WDCR/WQ0hWatchdog Configuration. Start value of the Message RAM Watchdog Counter. With the reset value of "00" the counter is disabled. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

25.7.6 CCCR Register (Offset = 18h) [Reset = 00000001h]

CCCR is shown in Table 25-17.

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DCAN CC Control Register

Table 25-17 CCCR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15NISOR/WQ0hNon ISO Operation. If this bit is set, the DCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 0 CAN FD frame format according to ISO 11898-1:2015 1 CAN FD frame format according to Bosch CAN FD Specification V1.0
14TXPR/WQ0hTransmit Pause. If this bit is set, the DCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame. 0 Transmit pause disabled 1 Transmit pause enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
13EFBIR/WQ0hEdge Filtering during Bus Integration 0 Edge filtering disabled 1 Two consecutive dominant tq required to detect an edge for hard synchronization Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
12PXHDR/WQ0hProtocol Exception Handling Disable 0 Protocol exception handling enabled 1 Protocol exception handling disabled Note: When protocol exception handling is disabled, the DCAN will transmit an error frame when it detects a protocol exception condition. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
11-10RESERVEDR0hReserved
9BRSER/WQ0hBit Rate Switch Enable 0 Bit rate switching for transmissions disabled 1 Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled FDOE = '0', BRSE is not evaluated. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
8FDOER/WQ0hFlexible Datarate Operation Enable 0 FD operation disabled 1 FD operation enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7TESTR/W1SQ0hTest Mode Enable 0 Normal operation, register TEST holds reset values 1 Test Mode, write access to register TEST enabled Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
6DARR/WQ0hDisable Automatic Retransmission 0 Automatic retransmission of messages not transmitted successfully enabled 1 Automatic retransmission disabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
5MONR/W1SQ0hBus Monitoring Mode. Bit MON can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time. 0 Bus Monitoring Mode is disabled 1 Bus Monitoring Mode is enabled Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
4CSRR/W0hClock Stop Request 0 No clock stop is requested 1 Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle.
3CSAR0hClock Stop Acknowledge 0 No clock stop acknowledged 1 DCAN may be set in power down by stopping the Host and CAN clocks
2ASMR/W1SQ0hRestricted Operation Mode. Bit ASM can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time. 0 Normal CAN operation 1 Restricted Operation Mode active Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1CCER/WQ0hConfiguration Change Enable 0 The CPU has no write access to the protected configuration registers 1 The CPU has write access to the protected configuration registers (while CCCR.INIT = '1') Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
0INITR/W1hInitialization 0 Normal Operation 1 Initialization is started Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value.

25.7.7 NBTP Register (Offset = 1Ch) [Reset = 06000A03h]

NBTP is shown in Table 25-18.

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This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programmed in the range of 4 to 385 time quanta. The CAN time quantum may be programmed in the range of 1 to 512 m_can_cclk periods. tq = (NBRP + 1) mtq. NTSEG1 is the sum of Prop_Seg and Phase_Seg1. NTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) (NTSEG1 + NTSEG2 + 3) tq or (functional values) (Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2) tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. Note: With a CAN clock of 8 MHz, the reset value of 0x06000A03 configures the DCAN for a bit rate of 500 kBit/s.

Table 25-18 NBTP Register Field Descriptions
BitFieldTypeResetDescription
31-25NSJWR/WQ3hNominal (Re)Synchronization Jump Width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
24-16NBRPR/WQ0hNominal Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-8NTSEG1R/WQAhNominal Time Segment Before Sample Point. Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7RESERVEDR0hReserved
6-0NTSEG2R/WQ3hNominal Time Segment After Sample Point. Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

25.7.8 TSCC Register (Offset = 20h) [Reset = 00000000h]

TSCC is shown in Table 25-19.

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DCAN Timestamp Counter Configuration

Table 25-19 TSCC Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-16TCPR/WQ0hTimestamp Counter Prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note: With CAN FD an external counter is required for timestamp generation (TSS = "10"). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2RESERVEDR0hReserved
1-0TSSR/WQ0hTimestamp Select 00 Timestamp counter value always 0x0000 01 Timestamp counter value incremented according to TCP 10 External timestamp counter value used 11 Same as "00" Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

25.7.9 TSCV Register (Offset = 24h) [Reset = 00000000h]

TSCV is shown in Table 25-20.

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DCAN Timestamp Counter Value

Table 25-20 TSCV Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0TSCR/W0hTimestamp Counter. The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = "01", the Timestamp Counter is incremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = "10", TSC reflects the External Timestamp Counter value, and a write access has no impact. Note: A "wrap around" is a change of the Timestamp Counter value from non-zero to zero not caused by write access to DCAN_TSCV.

25.7.10 TOCC Register (Offset = 28h) [Reset = FFFF0000h]

TOCC is shown in Table 25-21.

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DCAN Timeout Counter Configuration

Table 25-21 TOCC Register Field Descriptions
BitFieldTypeResetDescription
31-16TOPR/WQFFFFhTimeout Period. Start value of the Timeout Counter (down-counter). Configures the Timeout Period. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-3RESERVEDR0hReserved
2-1TOSR/WQ0hTimeout Select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. 00 Continuous operation 01 Timeout controlled by Tx Event FIFO 10 Timeout controlled by Rx FIFO 0 11 Timeout controlled by Rx FIFO 1 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
0ETOCR/WQ0hEnable Timeout Counter 0 Timeout Counter disabled 1 Timeout Counter enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

25.7.11 TOCV Register (Offset = 2Ch) [Reset = 0000FFFFh]

TOCV is shown in Table 25-22.

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DCAN Timeout Counter Value

Table 25-22 TOCV Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0TOCR/WFFFFhTimeout Counter. The Timeout Counter is decremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS.

25.7.12 ECR Register (Offset = 40h) [Reset = 00000000h]

ECR is shown in Table 25-23.

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DCAN Error Counter Register

Table 25-23 ECR Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16CELRC0hCAN Error Logging. The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.
15RPR0hReceive Error Passive 0 The Receive Error Counter is below the error passive level of 128 1 The Receive Error Counter has reached the error passive level of 128
14-8RECR0hReceive Error Counter. Actual state of the Receive Error Counter, values between 0 and 127. Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.
7-0TECR0hTransmit Error Counter. Actual state of the Transmit Error Counter, values between 0 and 255. Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.

25.7.13 PSR Register (Offset = 44h) [Reset = 00000707h]

PSR is shown in Table 25-24.

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DCAN Protocol Status Register

Table 25-24 PSR Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0hReserved
22-16TDCVR0hTransmitter Delay Compensation Value. Position of the secondary sample point, defined by the sum of the measured delay from the internal CAN TX signal to the internal CAN RX signal and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq.
15RESERVEDR0hReserved
14PXERC0hProtocol Exception Event 0 No protocol exception event occurred since last read access 1 Protocol exception event occurred
13RFDFRC0hReceived a CAN FD Message. This bit is set independent of acceptance filtering. 0 Since this bit was reset by the CPU, no CAN FD message has been received 1 Message in CAN FD format with FDF flag set has been received
12RBRSRC0hBRS Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering. 0 Last received CAN FD message did not have its BRS flag set 1 Last received CAN FD message had its BRS flag set
11RESIRC0hESI Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering. 0 Last received CAN FD message did not have its ESI flag set 1 Last received CAN FD message had its ESI flag set
10-8DLECRS7hData Phase Last Error Code. Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error.
7BOR0hBus_Off Status 0 The M_CAN is not Bus_Off 1 The M_CAN is in Bus_Off state
6EWR0hWarning Status 0 Both error counters are below the Error_Warning limit of 96 1 At least one of error counter has reached the Error_Warning limit of 96
5EPR0hError Passive 0 The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1 The M_CAN is in the Error_Passive state
4-3ACTR0hNode Activity. Monitors the module's CAN communication state. 00 Synchronizing - node is synchronizing on CAN communication 01 Idle - node is neither receiver nor transmitter 10 Receiver - node is operating as receiver 11 Transmitter - node is operating as transmitter Note: ACT is set to "00" by a Protocol Exception Event.
2-0LECRS7hLast Error Code. The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. 0 No Error: No error occurred since LEC has been reset by successful reception or transmission. 1 Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2 Form Error: A fixed format part of a received frame has the wrong format. 3 AckError: The message transmitted by the DCAN was not acknowledged by another node. 4 Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. 5 Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6 CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 7 NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last CPU read access to the Protocol Status Register. Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord, stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences.

25.7.14 TDCR Register (Offset = 48h) [Reset = 00000000h]

TDCR is shown in Table 25-25.

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DCAN Transmitter Delay Compensation Register

Table 25-25 TDCR Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hReserved
14-8TDCOR/WQ0hTransmitter Delay Compensation Offset. Offset value defining the distance between the measured delay from the internal CAN TX signal to the internal CAN RX signal and the secondary sample point. Valid values are 0 to 127 mtq. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7RESERVEDR0hReserved
6-0TDCFR/WQ0hTransmitter Delay Compensation Filter Window Length. Defines the minimum value for the SSP position, dominant edges on the internal CAN RX signal that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

25.7.15 IR Register (Offset = 50h) [Reset = 80000000h]

IR is shown in Table 25-26.

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The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. Aflag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. Ahard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signalled.

Table 25-26 IR Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29ARAR/W1C0hAccess to Reserved Address 0 No access to reserved address occurred 1 Access to reserved address occurred
28PEDR/W1C0hProtocol Error in Data Phase (Data Bit Time is used) 0 No protocol error in data phase 1 Protocol error in data phase detected (PSR.DLEC ? 0,7)
27PEAR/W1C0hProtocol Error in Arbitration Phase (Nominal Bit Time is used) 0 No protocol error in arbitration phase 1 Protocol error in arbitration phase detected (PSR.LEC ? 0,7)
26WDIR/W1C0hWatchdog Interrupt 0 No Message RAM Watchdog event occurred 1 Message RAM Watchdog event due to missing READY
25BOR/W1C0hBus_Off Status 0 Bus_Off status unchanged 1 Bus_Off status changed
24EWR/W1C0hWarning Status 0 Error_Warning status unchanged 1 Error_Warning status changed
23EPR/W1C0hError Passive 0 Error_Passive status unchanged 1 Error_Passive status changed
22ELOR/W1C0hError Logging Overflow 0 CAN Error Logging Counter did not overflow 1 Overflow of CAN Error Logging Counter occurred
21BEUR/W1C0hBit Error Uncorrected. Message RAM bit error detected, uncorrected. This bit is set when a double bit error is detected by the ECC aggregator attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data. 0 No bit error detected when reading from Message RAM 1 Bit error detected, uncorrected (e.g. parity logic)
20RESERVEDR0hReserved
19DRXR/W1C0hMessage Stored to Dedicated Rx Buffer. The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0 No Rx Buffer updated 1 At least one received message stored into an Rx Buffer
18TOOR/W1C0hTimeout Occurred 0 No timeout 1 Timeout reached
17MRAFR/W1C0hMessage RAM Access Failure. The flag is set, when the Rx Handler: - has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. - was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the DCAN is switched into Restricted Operation Mode. To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. 0 No Message RAM access failure occurred 1 Message RAM access failure occurred
16TSWR/W1C0hTimestamp Wraparound 0 No timestamp counter wrap-around 1 Timestamp counter wrapped around
15TEFLR/W1C0hTx Event FIFO Element Lost 0 No Tx Event FIFO element lost 1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero
14TEFFR/W1C0hTx Event FIFO Full 0 Tx Event FIFO not full 1 Tx Event FIFO full
13TEFWR/W1C0hTx Event FIFO Watermark Reached 0 Tx Event FIFO fill level below watermark 1 Tx Event FIFO fill level reached watermark
12TEFNR/W1C0hTx Event FIFO New Entry 0 Tx Event FIFO unchanged 1 Tx Handler wrote Tx Event FIFO element
11TFER/W1C0hTx FIFO Empty 0 Tx FIFO non-empty 1 Tx FIFO empty
10TCFR/W1C0hTransmission Cancellation Finished 0 No transmission cancellation finished 1 Transmission cancellation finished
9TCR/W1C0hTransmission Completed 0 No transmission completed 1 Transmission completed
8HPMR/W1C0hHigh Priority Message 0 No high priority message received 1 High priority message received
7RF1LR/W1C0hRx FIFO 1 Message Lost 0 No Rx FIFO 1 message lost 1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero
6RF1FR/W1C0hRx FIFO 1 Full 0 Rx FIFO 1 not full 1 Rx FIFO 1 full
5RF1WR/W1C0hRx FIFO 1 Watermark Reached 0 Rx FIFO 1 fill level below watermark 1 Rx FIFO 1 fill level reached watermark
4RF1NR/W1C0hRx FIFO 1 New Message 0 No new message written to Rx FIFO 1 1 New message written to Rx FIFO 1
3RF0LR/W1C0hRx FIFO 0 Message Lost 0 No Rx FIFO 0 message lost 1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero
2RF0FR/W1C0hRx FIFO 0 Full 0 Rx FIFO 0 not full 1 Rx FIFO 0 full
1RF0WR/W1C0hRx FIFO 0 Watermark Reached 0 Rx FIFO 0 fill level below watermark 1 Rx FIFO 0 fill level reached watermark
0RF0NR/W1C0hRx FIFO 0 New Message 0 No new message written to Rx FIFO 0 1 New message written to Rx FIFO 0

25.7.16 IE Register (Offset = 54h) [Reset = 00000000h]

IE is shown in Table 25-27.

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DCAN Interrupt Enable

Table 25-27 IE Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29ARAER/W0hAccess to Reserved Address Enable
28PEDER/W0hProtocol Error in Data Phase Enable
27PEAER/W0hProtocol Error in Arbitration Phase Enable
26WDIER/W0hWatchdog Interrupt Enable
25BOER/W0hBus_Off Status Enable
24EWER/W0hWarning Status Enable
23EPER/W0hError Passive Enable
22ELOER/W0hError Logging Overflow Enable
21BEUER/W0hBit Error Uncorrected Enable
20RESERVEDR/W0h
19DRXER/W0hMessage Stored to Dedicated Rx Buffer Enable
18TOOER/W0hTimeout Occurred Enable
17MRAFER/W0hMessage RAM Access Failure Enable
16TSWER/W0hTimestamp Wraparound Enable
15TEFLER/W0hTx Event FIFO Element Lost Enable
14TEFFER/W0hTx Event FIFO Full Enable
13TEFWER/W0hTx Event FIFO Watermark Reached Enable
12TEFNER/W0hTx Event FIFO New Entry Enable
11TFEER/W0hTx FIFO Empty Enable
10TCFER/W0hTransmission Cancellation Finished Enable
9TCER/W0hTransmission Completed Enable
8HPMER/W0hHigh Priority Message Enable
7RF1LER/W0hRx FIFO 1 Message Lost Enable
6RF1FER/W0hRx FIFO 1 Full Enable
5RF1WER/W0hRx FIFO 1 Watermark Reached Enable
4RF1NER/W0hRx FIFO 1 New Message Enable
3RF0LER/W0hRx FIFO 0 Message Lost Enable
2RF0FER/W0hRx FIFO 0 Full Enable
1RF0WER/W0hRx FIFO 0 Watermark Reached Enable
0RF0NER/W0hRx FIFO 0 New Message Enable

25.7.17 ILS Register (Offset = 58h) [Reset = 00000000h]

ILS is shown in Table 25-28.

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The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE.EINT0 and ILE.EINT1.

Table 25-28 ILS Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29ARALR/W0hAccess to Reserved Address Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
28PEDLR/W0hProtocol Error in Data Phase Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
27PEALR/W0hProtocol Error in Arbitration Phase Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
26WDILR/W0hWatchdog Interrupt Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
25BOLR/W0hBus_Off Status Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
24EWLR/W0hWarning Status Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
23EPLR/W0hError Passive Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
22ELOLR/W0hError Logging Overflow Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
21BEULR/W0hBit Error Uncorrected Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
20BECLR/W0hBit Error Corrected Line A separate interrupt line reserved for corrected bit errors is provided via the DCAN_ERROR_REGS. It advised for the user to use these registers and leave the DCAN_IE.BECE bit cleared to '0' (disabled), thereby relegating this bit to not applicable.
19DRXLR/W0hMessage Stored to Dedicated Rx Buffer Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
18TOOLR/W0hTimeout Occurred Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
17MRAFLR/W0hMessage RAM Access Failure Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
16TSWLR/W0hTimestamp Wraparound Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
15TEFLLR/W0hTx Event FIFO Element Lost Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
14TEFFLR/W0hTx Event FIFO Full Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
13TEFWLR/W0hTx Event FIFO Watermark Reached Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
12TEFNLR/W0hTx Event FIFO New Entry Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
11TFELR/W0hTx FIFO Empty Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
10TCFLR/W0hTransmission Cancellation Finished Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
9TCLR/W0hTransmission Completed Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
8HPMLR/W0hHigh Priority Message Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
7RF1LLR/W0hRx FIFO 1 Message Lost Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
6RF1FLR/W0hRx FIFO 1 Full Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
5RF1WLR/W0hRx FIFO 1 Watermark Reached Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
4RF1NLR/W0hRx FIFO 1 New Message Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
3RF0LLR/W0hRx FIFO 0 Message Lost Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
2RF0FLR/W0hRx FIFO 0 Full Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
1RF0WLR/W0hRx FIFO 0 Watermark Reached Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1
0RF0NLR/W0hRx FIFO 0 New Message Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1

25.7.18 ILE Register (Offset = 5Ch) [Reset = 00000000h]

ILE is shown in Table 25-29.

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DCAN Interrupt Line Enable

Table 25-29 ILE Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1EINT1R/W0hEnable Interrupt Line 1 0 Interrupt Line 1 is disabled 1 Interrupt Line 1 is enabled
0EINT0R/W0hEnable Interrupt Line 0 0 Interrupt Line 0 is disabled 1 Interrupt Line 0 is enabled

25.7.19 GFC Register (Offset = 80h) [Reset = 00000000h]

GFC is shown in Table 25-30.

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DCAN Global Filter Configuration

Table 25-30 GFC Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-4ANFSR/WQ0hAccept Non-matching Frames Standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 00 Accept in Rx FIFO 0 01 Accept in Rx FIFO 1 10 Reject 11 Reject Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
3-2ANFER/WQ0hAccept Non-matching Frames Extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 00 Accept in Rx FIFO 0 01 Accept in Rx FIFO 1 10 Reject 11 Reject Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1RRFSR/WQ0hReject Remote Frames Standard 0 Filter remote frames with 11-bit standard IDs 1 Reject all remote frames with 11-bit standard IDs Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
0RRFER/WQ0hReject Remote Frames Extended 0 Filter remote frames with 29-bit extended IDs 1 Reject all remote frames with 29-bit extended IDs Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

25.7.20 SIDFC Register (Offset = 84h) [Reset = 00000000h]

SIDFC is shown in Table 25-31.

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DCAN Standard ID Filter Configuration

Table 25-31 SIDFC Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16LSSR/WQ0hList Size Standard 0 No standard Message ID filter 1-128 Number of standard Message ID filter elements >128 Values greater than 128 are interpreted as 128
15-2FLSSAR/WQ0hFilter List Standard Start Address. Start address of standard Message ID filter list (32-bit word address).
1-0RESERVEDR0hReserved

25.7.21 XIDFC Register (Offset = 88h) [Reset = 00000000h]

XIDFC is shown in Table 25-32.

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DCAN Extended ID Filter Configuration

Table 25-32 XIDFC Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0hReserved
22-16LSER/WQ0hList Size Extended 0 No extended Message ID filter 1-64 Number of extended Message ID filter elements >64 Values greater than 64 are interpreted as 64 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2FLESAR/WQ0hFilter List Extended Start Address. Start address of extended Message ID filter list (32-bit word address). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1-0RESERVEDR0hReserved

25.7.22 XIDAM Register (Offset = 90h) [Reset = 1FFFFFFFh]

XIDAM is shown in Table 25-33.

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DCAN Extended ID and Mask

Table 25-33 XIDAM Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-0EIDMR/WQ1FFFFFFFhExtended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

25.7.23 HPMS Register (Offset = 94h) [Reset = 00000000h]

HPMS is shown in Table 25-34.

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This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.

Table 25-34 HPMS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15FLSTR0hFilter List. Indicates the filter list of the matching filter element. 0 Standard Filter List 1 Extended Filter List
14-8FIDXR0hFilter Index. Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1.
7-6MSIR0hMessage Storage Indicator 00 No FIFO selected 01 FIFO message lost 10 Message stored in FIFO 0 11 Message stored in FIFO 1
5-0BIDXR0hBuffer Index. Index of Rx FIFO element to which the message was stored. Only valid when MSI(1) = '1'.

25.7.24 NDAT1 Register (Offset = 98h) [Reset = 00000000h]

NDAT1 is shown in Table 25-35.

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DCAN New Data 1

Table 25-35 NDAT1 Register Field Descriptions
BitFieldTypeResetDescription
31ND31R/W1C0hNew Data RX Buffer 31 0 Rx Buffer not updated 1 Rx Buffer updated from new message
30ND30R/W1C0hNew Data RX Buffer 30 0 Rx Buffer not updated 1 Rx Buffer updated from new message
29ND29R/W1C0hNew Data RX Buffer 29 0 Rx Buffer not updated 1 Rx Buffer updated from new message
28ND28R/W1C0hNew Data RX Buffer 28 0 Rx Buffer not updated 1 Rx Buffer updated from new message
27ND27R/W1C0hNew Data RX Buffer 27 0 Rx Buffer not updated 1 Rx Buffer updated from new message
26ND26R/W1C0hNew Data RX Buffer 26 0 Rx Buffer not updated 1 Rx Buffer updated from new message
25ND25R/W1C0hNew Data RX Buffer 25 0 Rx Buffer not updated 1 Rx Buffer updated from new message
24ND24R/W1C0hNew Data RX Buffer 24 0 Rx Buffer not updated 1 Rx Buffer updated from new message
23ND23R/W1C0hNew Data RX Buffer 23 0 Rx Buffer not updated 1 Rx Buffer updated from new message
22ND22R/W1C0hNew Data RX Buffer 22 0 Rx Buffer not updated 1 Rx Buffer updated from new message
21ND21R/W1C0hNew Data RX Buffer 21 0 Rx Buffer not updated 1 Rx Buffer updated from new message
20ND20R/W1C0hNew Data RX Buffer 20 0 Rx Buffer not updated 1 Rx Buffer updated from new message
19ND19R/W1C0hNew Data RX Buffer 19 0 Rx Buffer not updated 1 Rx Buffer updated from new message
18ND18R/W1C0hNew Data RX Buffer 18 0 Rx Buffer not updated 1 Rx Buffer updated from new message
17ND17R/W1C0hNew Data RX Buffer 17 0 Rx Buffer not updated 1 Rx Buffer updated from new message
16ND16R/W1C0hNew Data RX Buffer 16 0 Rx Buffer not updated 1 Rx Buffer updated from new message
15ND15R/W1C0hNew Data RX Buffer 15 0 Rx Buffer not updated 1 Rx Buffer updated from new message
14ND14R/W1C0hNew Data RX Buffer 14 0 Rx Buffer not updated 1 Rx Buffer updated from new message
13ND13R/W1C0hNew Data RX Buffer 13 0 Rx Buffer not updated 1 Rx Buffer updated from new message
12ND12R/W1C0hNew Data RX Buffer 12 0 Rx Buffer not updated 1 Rx Buffer updated from new message
11ND11R/W1C0hNew Data RX Buffer 11 0 Rx Buffer not updated 1 Rx Buffer updated from new message
10ND10R/W1C0hNew Data RX Buffer 10 0 Rx Buffer not updated 1 Rx Buffer updated from new message
9ND9R/W1C0hNew Data RX Buffer 9 0 Rx Buffer not updated 1 Rx Buffer updated from new message
8ND8R/W1C0hNew Data RX Buffer 8 0 Rx Buffer not updated 1 Rx Buffer updated from new message
7ND7R/W1C0hNew Data RX Buffer 7 0 Rx Buffer not updated 1 Rx Buffer updated from new message
6ND6R/W1C0hNew Data RX Buffer 6 0 Rx Buffer not updated 1 Rx Buffer updated from new message
5ND5R/W1C0hNew Data RX Buffer 5 0 Rx Buffer not updated 1 Rx Buffer updated from new message
4ND4R/W1C0hNew Data RX Buffer 4 0 Rx Buffer not updated 1 Rx Buffer updated from new message
3ND3R/W1C0hNew Data RX Buffer 3 0 Rx Buffer not updated 1 Rx Buffer updated from new message
2ND2R/W1C0hNew Data RX Buffer 2 0 Rx Buffer not updated 1 Rx Buffer updated from new message
1ND1R/W1C0hNew Data RX Buffer 1 0 Rx Buffer not updated 1 Rx Buffer updated from new message
0ND0R/W1C0hNew Data RX Buffer 0 0 Rx Buffer not updated 1 Rx Buffer updated from new message

25.7.25 NDAT2 Register (Offset = 9Ch) [Reset = 00000000h]

NDAT2 is shown in Table 25-36.

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DCAN New Data 2

Table 25-36 NDAT2 Register Field Descriptions
BitFieldTypeResetDescription
31ND63R/W1C0hNew Data RX Buffer 63 0 Rx Buffer not updated 1 Rx Buffer updated from new message
30ND62R/W1C0hNew Data RX Buffer 62 0 Rx Buffer not updated 1 Rx Buffer updated from new message
29ND61R/W1C0hNew Data RX Buffer 61 0 Rx Buffer not updated 1 Rx Buffer updated from new message
28ND60R/W1C0hNew Data RX Buffer 60 0 Rx Buffer not updated 1 Rx Buffer updated from new message
27ND59R/W1C0hNew Data RX Buffer 59 0 Rx Buffer not updated 1 Rx Buffer updated from new message
26ND58R/W1C0hNew Data RX Buffer 58 0 Rx Buffer not updated 1 Rx Buffer updated from new message
25ND57R/W1C0hNew Data RX Buffer 57 0 Rx Buffer not updated 1 Rx Buffer updated from new message
24ND56R/W1C0hNew Data RX Buffer 56 0 Rx Buffer not updated 1 Rx Buffer updated from new message
23ND55R/W1C0hNew Data RX Buffer 55 0 Rx Buffer not updated 1 Rx Buffer updated from new message
22ND54R/W1C0hNew Data RX Buffer 54 0 Rx Buffer not updated 1 Rx Buffer updated from new message
21ND53R/W1C0hNew Data RX Buffer 53 0 Rx Buffer not updated 1 Rx Buffer updated from new message
20ND52R/W1C0hNew Data RX Buffer 52 0 Rx Buffer not updated 1 Rx Buffer updated from new message
19ND51R/W1C0hNew Data RX Buffer 51 0 Rx Buffer not updated 1 Rx Buffer updated from new message
18ND50R/W1C0hNew Data RX Buffer 50 0 Rx Buffer not updated 1 Rx Buffer updated from new message
17ND49R/W1C0hNew Data RX Buffer 49 0 Rx Buffer not updated 1 Rx Buffer updated from new message
16ND48R/W1C0hNew Data RX Buffer 48 0 Rx Buffer not updated 1 Rx Buffer updated from new message
15ND47R/W1C0hNew Data RX Buffer 47 0 Rx Buffer not updated 1 Rx Buffer updated from new message
14ND46R/W1C0hNew Data RX Buffer 46 0 Rx Buffer not updated 1 Rx Buffer updated from new message
13ND45R/W1C0hNew Data RX Buffer 45 0 Rx Buffer not updated 1 Rx Buffer updated from new message
12ND44R/W1C0hNew Data RX Buffer 44 0 Rx Buffer not updated 1 Rx Buffer updated from new message
11ND43R/W1C0hNew Data RX Buffer 43 0 Rx Buffer not updated 1 Rx Buffer updated from new message
10ND42R/W1C0hNew Data RX Buffer 42 0 Rx Buffer not updated 1 Rx Buffer updated from new message
9ND41R/W1C0hNew Data RX Buffer 41 0 Rx Buffer not updated 1 Rx Buffer updated from new message
8ND40R/W1C0hNew Data RX Buffer 40 0 Rx Buffer not updated 1 Rx Buffer updated from new message
7ND39R/W1C0hNew Data RX Buffer 39 0 Rx Buffer not updated 1 Rx Buffer updated from new message
6ND38R/W1C0hNew Data RX Buffer 38 0 Rx Buffer not updated 1 Rx Buffer updated from new message
5ND37R/W1C0hNew Data RX Buffer 37 0 Rx Buffer not updated 1 Rx Buffer updated from new message
4ND36R/W1C0hNew Data RX Buffer 36 0 Rx Buffer not updated 1 Rx Buffer updated from new message
3ND35R/W1C0hNew Data RX Buffer 35 0 Rx Buffer not updated 1 Rx Buffer updated from new message
2ND34R/W1C0hNew Data RX Buffer 34 0 Rx Buffer not updated 1 Rx Buffer updated from new message
1ND33R/W1C0hNew Data RX Buffer 33 0 Rx Buffer not updated 1 Rx Buffer updated from new message
0ND32R/W1C0hNew Data RX Buffer 32 0 Rx Buffer not updated 1 Rx Buffer updated from new message

25.7.26 RXF0C Register (Offset = A0h) [Reset = 00000000h]

RXF0C is shown in Table 25-37.

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DCAN Rx FIFO 0 Configuration

Table 25-37 RXF0C Register Field Descriptions
BitFieldTypeResetDescription
31F0OMR/WQ0hFIFO 0 Operation Mode. FIFO 0 can be operated in blocking or in overwrite mode. 0 FIFO 0 blocking mode 1 FIFO 0 overwrite mode Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
30-24F0WMR/WQ0hRx FIFO 0 Watermark 0 Watermark interrupt disabled 1-64 Level for Rx FIFO 0 watermark interrupt (IR.RF0W) >64 Watermark interrupt disabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
23RESERVEDR0hReserved
22-16F0SR/WQ0hRx FIFO 0 Size. The Rx FIFO 0 elements are indexed from 0 to F0S-1. 0 No Rx FIFO 0 1-64 Number of Rx FIFO 0 elements >64 Values greater than 64 are interpreted as 64 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2F0SAR/WQ0hRx FIFO 0 Start Address. Start address of Rx FIFO 0 in Message RAM (32-bit word address). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1-0RESERVEDR0hReserved

25.7.27 RXF0S Register (Offset = A4h) [Reset = 00000000h]

RXF0S is shown in Table 25-38.

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DCAN Rx FIFO 0 Status

Table 25-38 RXF0S Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25RF0LR0hRx FIFO 0 Message Lost. This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. 0 No Rx FIFO 0 message lost 1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero Note: Overwriting the oldest message when RXF0C.F0OM = '1' will not set this flag.
24F0FR0hRx FIFO 0 Full 0 Rx FIFO 0 not full 1 Rx FIFO 0 full
23-22RESERVEDR0hReserved
21-16F0PIR0hRx FIFO 0 Put Index. Rx FIFO 0 write index pointer, range 0 to 63.
15-14RESERVEDR0hReserved
13-8F0GIR0hRx FIFO 0 Get Index. Rx FIFO 0 read index pointer, range 0 to 63.
7RESERVEDR0hReserved
6-0F0FLR0hRx FIFO 0 Fill Level. Number of elements stored in Rx FIFO 0, range 0 to 64.

25.7.28 RXF0A Register (Offset = A8h) [Reset = 00000000h]

RXF0A is shown in Table 25-39.

Return to the Summary Table.

DCAN Rx FIFO 0 Acknowledge

Table 25-39 RXF0A Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0F0AIR/W0hRx FIFO 0 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL.

25.7.29 RXBC Register (Offset = ACh) [Reset = 00000000h]

RXBC is shown in Table 25-40.

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DCAN Rx Buffer Configuration

Table 25-40 RXBC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-2RBSAR/WQ0hRx Buffer Start Address. Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). +I466
1-0RESERVEDR0hReserved

25.7.30 RXF1C Register (Offset = B0h) [Reset = 00000000h]

RXF1C is shown in Table 25-41.

Return to the Summary Table.

DCAN Rx FIFO 1 Configuration

Table 25-41 RXF1C Register Field Descriptions
BitFieldTypeResetDescription
31F1OMR/WQ0hFIFO 1 Operation Mode. FIFO 1 can be operated in blocking or in overwrite mode. 0 FIFO 1 blocking mode 1 FIFO 1 overwrite mode Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
30-24F1WMR/WQ0hRx FIFO 1 Watermark 0 Watermark interrupt disabled 1-64 Level for Rx FIFO 1 watermark interrupt (IR.RF1W) >64 Watermark interrupt disabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
23RESERVEDR0hReserved
22-16F1SR/WQ0hRx FIFO 1 Size. The Rx FIFO 1 elements are indexed from 0 to F1S - 1. 0 No Rx FIFO 1 1-64 Number of Rx FIFO 1 elements >64 Values greater than 64 are interpreted as 64 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2F1SAR/WQ0hRx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address).
1-0RESERVEDR0hReserved

25.7.31 RXF1S Register (Offset = B4h) [Reset = 00000000h]

RXF1S is shown in Table 25-42.

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DCAN Rx FIFO 1 Status

Table 25-42 RXF1S Register Field Descriptions
BitFieldTypeResetDescription
31-30DMSR0hDebug Message Status 00 Idle state, wait for reception of debug messages, DMA request is cleared 01 Debug message A received 10 Debug messages A, B received 11 Debug messages A, B, C received, DMA request is set
29-26RESERVEDR0hReserved
25RF1LR0hRx FIFO 1 Message Lost. This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. 0 No Rx FIFO 1 message lost 1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero Note: Overwriting the oldest message when RXF1C.F1OM = '1' will not set this flag.
24F1FR0hRx FIFO 1 Full 0 Rx FIFO 1 not full 1 Rx FIFO 1 full
23-22RESERVEDR0hReserved
21-16F1PIR0hRx FIFO 1 Put Index. Rx FIFO 1 write index pointer, range 0 to 63.
15-14RESERVEDR0hReserved
13-8F1GIR0hRx FIFO 1 Get Index. Rx FIFO 1 read index pointer, range 0 to 63.
7RESERVEDR0hReserved
6-0F1FLR0hRx FIFO 1 Fill Level. Number of elements stored in Rx FIFO 1, range 0 to 64.

25.7.32 RXF1A Register (Offset = B8h) [Reset = 00000000h]

RXF1A is shown in Table 25-43.

Return to the Summary Table.

DCAN Rx FIFO 1 Acknowledge

Table 25-43 RXF1A Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0F1AIR/W0hRx FIFO 1 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL.

25.7.33 RXESC Register (Offset = BCh) [Reset = 00000000h]

RXESC is shown in Table 25-44.

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Configures the number of data bytes belonging to an Rx Buffer / Rx FIFO element. Data field sizes >8 bytes are intended for CAN FD operation only.

Table 25-44 RXESC Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10-8RBDSR/WQ0hRx Buffer Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7RESERVEDR0hReserved
6-4F1DSR/WQ0hRx FIFO 1 Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
3RESERVEDR0hReserved
2-0F0DSR/WQ0hRx FIFO 0 Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

25.7.34 TXBC Register (Offset = C0h) [Reset = 00000000h]

TXBC is shown in Table 25-45.

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DCAN Tx Buffer Configuration

Table 25-45 TXBC Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30TFQMR/WQ0hTx FIFO/Queue Mode 0 Tx FIFO operation 1 Tx Queue operation Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
29-24TFQSR/WQ0hTransmit FIFO/Queue Size 0 No Tx FIFO/Queue 1-32 Number of Tx Buffers used for Tx FIFO/Queue >32 Values greater than 32 are interpreted as 32 Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
23-22RESERVEDR0hReserved
21-16NDTBR/WQ0hNumber of Dedicated Transmit Buffers 0 No Dedicated Tx Buffers 1-32 Number of Dedicated Tx Buffers >32 Values greater than 32 are interpreted as 32 Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2TBSAR/WQ0hTx Buffers Start Address. Start address of Tx Buffers section in Message RAM (32-bit word address). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1-0RESERVEDR0hReserved

25.7.35 TXFQS Register (Offset = C4h) [Reset = 00000000h]

TXFQS is shown in Table 25-46.

Return to the Summary Table.

The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated).

Table 25-46 TXFQS Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0hReserved
21TFQFR0hTx FIFO/Queue Full 0 Tx FIFO/Queue not full 1 Tx FIFO/Queue full
20-16TFQPR0hTx FIFO/Queue Put Index. Tx FIFO/Queue write index pointer, range 0 to 31. Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO.
15-13RESERVEDR0hReserved
12-8TFGIR0hTx FIFO Get Index. Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1'). Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO.
7-6RESERVEDR0hReserved
5-0TFFLR0hTx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1').

25.7.36 TXESC Register (Offset = C8h) [Reset = 00000000h]

TXESC is shown in Table 25-47.

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Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only.

Table 25-47 TXESC Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0TBDSR/WQ0hTx Buffer Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as "0xCC" (padding bytes). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

25.7.37 TXBRPAP Register (Offset = CCh) [Reset = 00000000h]

TXBRPAP is shown in Table 25-48.

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DCAN Tx Buffer Request Pending

Table 25-48 TXBRPAP Register Field Descriptions
BitFieldTypeResetDescription
31TRP31R0hTransmission Request Pending 31. See description for bit 0.
30TRP30R0hTransmission Request Pending 30. See description for bit 0.
29TRP29R0hTransmission Request Pending 29. See description for bit 0.
28TRP28R0hTransmission Request Pending 28. See description for bit 0.
27TRP27R0hTransmission Request Pending 27. See description for bit 0.
26TRP26R0hTransmission Request Pending 26. See description for bit 0.
25TRP25R0hTransmission Request Pending 25. See description for bit 0.
24TRP24R0hTransmission Request Pending 24. See description for bit 0.
23TRP23R0hTransmission Request Pending 23. See description for bit 0.
22TRP22R0hTransmission Request Pending 22. See description for bit 0.
21TRP21R0hTransmission Request Pending 21. See description for bit 0.
20TRP20R0hTransmission Request Pending 20. See description for bit 0.
19TRP19R0hTransmission Request Pending 19. See description for bit 0.
18TRP18R0hTransmission Request Pending 18. See description for bit 0.
17TRP17R0hTransmission Request Pending 17. See description for bit 0.
16TRP16R0hTransmission Request Pending 16. See description for bit 0.
15TRP15R0hTransmission Request Pending 15. See description for bit 0.
14TRP14R0hTransmission Request Pending 14. See description for bit 0.
13TRP13R0hTransmission Request Pending 13. See description for bit 0.
12TRP12R0hTransmission Request Pending 12. See description for bit 0.
11TRP11R0hTransmission Request Pending 11. See description for bit 0.
10TRP10R0hTransmission Request Pending 10. See description for bit 0.
9TRP9R0hTransmission Request Pending 9. See description for bit 0.
8TRP8R0hTransmission Request Pending 8. See description for bit 0.
7TRP7R0hTransmission Request Pending 7. See description for bit 0.
6TRP6R0hTransmission Request Pending 6. See description for bit 0.
5TRP5R0hTransmission Request Pending 5. See description for bit 0.
4TRP4R0hTransmission Request Pending 4. See description for bit 0.
3TRP3R0hTransmission Request Pending 3. See description for bit 0.
2TRP2R0hTransmission Request Pending 2. See description for bit 0.
1TRP1R0hTransmission Request Pending 1. See description for bit 0.
0TRP0R0hTransmission Request Pending 0. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR. TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signalled via TXBCF - after successful transmission together with the corresponding TXBTO bit - when the transmission has not yet been started at the point of cancellation - when the transmission has been aborted due to lost arbitration - when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. 0 No transmission request pending 1 Transmission request pending Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset.

25.7.38 TXBAR Register (Offset = D0h) [Reset = 00000000h]

TXBAR is shown in Table 25-49.

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DCAN Tx Buffer Add Request

Table 25-49 TXBAR Register Field Descriptions
BitFieldTypeResetDescription
31AR31R/WQ0hAdd Request 31. See description for bit 0.
30AR30R/WQ0hAdd Request 30. See description for bit 0.
29AR29R/WQ0hAdd Request 29. See description for bit 0.
28AR28R/WQ0hAdd Request 28. See description for bit 0.
27AR27R/WQ0hAdd Request 27. See description for bit 0.
26AR26R/WQ0hAdd Request 26. See description for bit 0.
25AR25R/WQ0hAdd Request 25. See description for bit 0.
24AR24R/WQ0hAdd Request 24. See description for bit 0.
23AR23R/WQ0hAdd Request 23. See description for bit 0.
22AR22R/WQ0hAdd Request 22. See description for bit 0.
21AR21R/WQ0hAdd Request 21. See description for bit 0.
20AR20R/WQ0hAdd Request 20. See description for bit 0.
19AR19R/WQ0hAdd Request 19. See description for bit 0.
18AR18R/WQ0hAdd Request 18. See description for bit 0.
17AR17R/WQ0hAdd Request 17. See description for bit 0.
16AR16R/WQ0hAdd Request 16. See description for bit 0.
15AR15R/WQ0hAdd Request 15. See description for bit 0.
14AR14R/WQ0hAdd Request 14. See description for bit 0.
13AR13R/WQ0hAdd Request 13. See description for bit 0.
12AR12R/WQ0hAdd Request 12. See description for bit 0.
11AR11R/WQ0hAdd Request 11. See description for bit 0.
10AR10R/WQ0hAdd Request 10. See description for bit 0.
9AR9R/WQ0hAdd Request 9. See description for bit 0.
8AR8R/WQ0hAdd Request 8. See description for bit 0.
7AR7R/WQ0hAdd Request 7. See description for bit 0.
6AR6R/WQ0hAdd Request 6. See description for bit 0.
5AR5R/WQ0hAdd Request 5. See description for bit 0.
4AR4R/WQ0hAdd Request 4. See description for bit 0.
3AR3R/WQ0hAdd Request 3. See description for bit 0.
2AR2R/WQ0hAdd Request 2. See description for bit 0.
1AR1R/WQ0hAdd Request 1. See description for bit 0.
0AR0R/WQ0hAdd Request 0. Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0 No transmission request added 1 Transmission requested added Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. Qualified Write is possible only with CCCR.CCE='0'

25.7.39 TXBCR Register (Offset = D4h) [Reset = 00000000h]

TXBCR is shown in Table 25-50.

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DCAN Tx Buffer Cancellation Request

Table 25-50 TXBCR Register Field Descriptions
BitFieldTypeResetDescription
31CR31R/WQ0hCancellation Request 31. See description for bit 0.
30CR30R/WQ0hCancellation Request 30. See description for bit 0.
29CR29R/WQ0hCancellation Request 29. See description for bit 0.
28CR28R/WQ0hCancellation Request 28. See description for bit 0.
27CR27R/WQ0hCancellation Request 27. See description for bit 0.
26CR26R/WQ0hCancellation Request 26. See description for bit 0.
25CR25R/WQ0hCancellation Request 25. See description for bit 0.
24CR24R/WQ0hCancellation Request 24. See description for bit 0.
23CR23R/WQ0hCancellation Request 23. See description for bit 0.
22CR22R/WQ0hCancellation Request 22. See description for bit 0.
21CR21R/WQ0hCancellation Request 21. See description for bit 0.
20CR20R/WQ0hCancellation Request 20. See description for bit 0.
19CR19R/WQ0hCancellation Request 19. See description for bit 0.
18CR18R/WQ0hCancellation Request 18. See description for bit 0.
17CR17R/WQ0hCancellation Request 17. See description for bit 0.
16CR16R/WQ0hCancellation Request 16. See description for bit 0.
15CR15R/WQ0hCancellation Request 15. See description for bit 0.
14CR14R/WQ0hCancellation Request 14. See description for bit 0.
13CR13R/WQ0hCancellation Request 13. See description for bit 0.
12CR12R/WQ0hCancellation Request 12. See description for bit 0.
11CR11R/WQ0hCancellation Request 11. See description for bit 0.
10CR10R/WQ0hCancellation Request 10. See description for bit 0.
9CR9R/WQ0hCancellation Request 9. See description for bit 0.
8CR8R/WQ0hCancellation Request 8. See description for bit 0.
7CR7R/WQ0hCancellation Request 7. See description for bit 0.
6CR6R/WQ0hCancellation Request 6. See description for bit 0.
5CR5R/WQ0hCancellation Request 5. See description for bit 0.
4CR4R/WQ0hCancellation Request 4. See description for bit 0.
3CR3R/WQ0hCancellation Request 3. See description for bit 0.
2CR2R/WQ0hCancellation Request 2. See description for bit 0.
1CR1R/WQ0hCancellation Request 1. See description for bit 0.
0CR0R/WQ0hCancellation Request 0. Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. 0 No cancellation pending 1 Cancellation pending Qualified Write is possible only with CCCR.CCE='0'

25.7.40 TXBTO Register (Offset = D8h) [Reset = 00000000h]

TXBTO is shown in Table 25-51.

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DCAN Tx Buffer Transmission Occurred

Table 25-51 TXBTO Register Field Descriptions
BitFieldTypeResetDescription
31TO31R0hTransmission Occurred 31. See description for bit 0.
30TO30R0hTransmission Occurred 30. See description for bit 0.
29TO29R0hTransmission Occurred 29. See description for bit 0.
28TO28R0hTransmission Occurred 28. See description for bit 0.
27TO27R0hTransmission Occurred 27. See description for bit 0.
26TO26R0hTransmission Occurred 26. See description for bit 0.
25TO25R0hTransmission Occurred 25. See description for bit 0.
24TO24R0hTransmission Occurred 24. See description for bit 0.
23TO23R0hTransmission Occurred 23. See description for bit 0.
22TO22R0hTransmission Occurred 22. See description for bit 0.
21TO21R0hTransmission Occurred 21. See description for bit 0.
20TO20R0hTransmission Occurred 20. See description for bit 0.
19TO19R0hTransmission Occurred 19. See description for bit 0.
18TO18R0hTransmission Occurred 18. See description for bit 0.
17TO17R0hTransmission Occurred 17. See description for bit 0.
16TO16R0hTransmission Occurred 16. See description for bit 0.
15TO15R0hTransmission Occurred 15. See description for bit 0.
14TO14R0hTransmission Occurred 14. See description for bit 0.
13TO13R0hTransmission Occurred 13. See description for bit 0.
12TO12R0hTransmission Occurred 12. See description for bit 0.
11TO11R0hTransmission Occurred 11. See description for bit 0.
10TO10R0hTransmission Occurred 10. See description for bit 0.
9TO9R0hTransmission Occurred 9. See description for bit 0.
8TO8R0hTransmission Occurred 8. See description for bit 0.
7TO7R0hTransmission Occurred 7. See description for bit 0.
6TO6R0hTransmission Occurred 6. See description for bit 0.
5TO5R0hTransmission Occurred 5. See description for bit 0.
4TO4R0hTransmission Occurred 4. See description for bit 0.
3TO3R0hTransmission Occurred 3. See description for bit 0.
2TO2R0hTransmission Occurred 2. See description for bit 0.
1TO1R0hTransmission Occurred 1. See description for bit 0.
0TO0R0hTransmission Occurred 0. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0 No transmission occurred 1 Transmission occurred

25.7.41 TXBCF Register (Offset = DCh) [Reset = 00000000h]

TXBCF is shown in Table 25-52.

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DCAN Tx Buffer Cancellation Finished

Table 25-52 TXBCF Register Field Descriptions
BitFieldTypeResetDescription
31CF31R0hCancellation Finished 31. See description for bit 0.
30CF30R0hCancellation Finished 30. See description for bit 0.
29CF29R0hCancellation Finished 29. See description for bit 0.
28CF28R0hCancellation Finished 28. See description for bit 0.
27CF27R0hCancellation Finished 27. See description for bit 0.
26CF26R0hCancellation Finished 26. See description for bit 0.
25CF25R0hCancellation Finished 25. See description for bit 0.
24CF24R0hCancellation Finished 24. See description for bit 0.
23CF23R0hCancellation Finished 23. See description for bit 0.
22CF22R0hCancellation Finished 22. See description for bit 0.
21CF21R0hCancellation Finished 21. See description for bit 0.
20CF20R0hCancellation Finished 20. See description for bit 0.
19CF19R0hCancellation Finished 19. See description for bit 0.
18CF18R0hCancellation Finished 18. See description for bit 0.
17CF17R0hCancellation Finished 17. See description for bit 0.
16CF16R0hCancellation Finished 16. See description for bit 0.
15CF15R0hCancellation Finished 15. See description for bit 0.
14CF14R0hCancellation Finished 14. See description for bit 0.
13CF13R0hCancellation Finished 13. See description for bit 0.
12CF12R0hCancellation Finished 12. See description for bit 0.
11CF11R0hCancellation Finished 11. See description for bit 0.
10CF10R0hCancellation Finished 10. See description for bit 0.
9CF9R0hCancellation Finished 9. See description for bit 0.
8CF8R0hCancellation Finished 8. See description for bit 0.
7CF7R0hCancellation Finished 7. See description for bit 0.
6CF6R0hCancellation Finished 6. See description for bit 0.
5CF5R0hCancellation Finished 5. See description for bit 0.
4CF4R0hCancellation Finished 4. See description for bit 0.
3CF3R0hCancellation Finished 3. See description for bit 0.
2CF2R0hCancellation Finished 2. See description for bit 0.
1CF1R0hCancellation Finished 1. See description for bit 0.
0CF0R0hCancellation Finished 0. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0 No transmit buffer cancellation 1 Transmit buffer cancellation finished

25.7.42 TXTIE Register (Offset = E0h) [Reset = 00000000h]

TXTIE is shown in Table 25-53.

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DCAN Tx Buffer Transmission Interrupt Enable

Table 25-53 TXTIE Register Field Descriptions
BitFieldTypeResetDescription
31TIE31R/W0hTransmission Interrupt Enable 31. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
30TIE30R/W0hTransmission Interrupt Enable 30. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
29TIE29R/W0hTransmission Interrupt Enable 29. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
28TIE28R/W0hTransmission Interrupt Enable 28. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
27TIE27R/W0hTransmission Interrupt Enable 27. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
26TIE26R/W0hTransmission Interrupt Enable 26. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
25TIE25R/W0hTransmission Interrupt Enable 25. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
24TIE24R/W0hTransmission Interrupt Enable 24. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
23TIE23R/W0hTransmission Interrupt Enable 23. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
22TIE22R/W0hTransmission Interrupt Enable 22. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
21TIE21R/W0hTransmission Interrupt Enable 21. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
20TIE20R/W0hTransmission Interrupt Enable 20. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
19TIE19R/W0hTransmission Interrupt Enable 19. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
18TIE18R/W0hTransmission Interrupt Enable 18. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
17TIE17R/W0hTransmission Interrupt Enable 17. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
16TIE16R/W0hTransmission Interrupt Enable 16. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
15TIE15R/W0hTransmission Interrupt Enable 15. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
14TIE14R/W0hTransmission Interrupt Enable 14. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
13TIE13R/W0hTransmission Interrupt Enable 13. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
12TIE12R/W0hTransmission Interrupt Enable 12. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
11TIE11R/W0hTransmission Interrupt Enable 11. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
10TIE10R/W0hTransmission Interrupt Enable 10. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
9TIE9R/W0hTransmission Interrupt Enable 9. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
8TIE8R/W0hTransmission Interrupt Enable 8. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
7TIE7R/W0hTransmission Interrupt Enable 7. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
6TIE6R/W0hTransmission Interrupt Enable 6. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
5TIE5R/W0hTransmission Interrupt Enable 5. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
4TIE4R/W0hTransmission Interrupt Enable 4. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
3TIE3R/W0hTransmission Interrupt Enable 3. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
2TIE2R/W0hTransmission Interrupt Enable 2. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
1TIE1R/W0hTransmission Interrupt Enable 1. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable
0TIE0R/W0hTransmission Interrupt Enable 0. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable

25.7.43 TXBCIE Register (Offset = E4h) [Reset = 00000000h]

TXBCIE is shown in Table 25-54.

Return to the Summary Table.

DCAN Tx Buffer Cancellation Finished Interrupt Enable

Table 25-54 TXBCIE Register Field Descriptions
BitFieldTypeResetDescription
31CFIE31R/W0hCancellation Finished Interrupt Enable 31. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
30CFIE30R/W0hCancellation Finished Interrupt Enable 30. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
29CFIE29R/W0hCancellation Finished Interrupt Enable 29. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
28CFIE28R/W0hCancellation Finished Interrupt Enable 28. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
27CFIE27R/W0hCancellation Finished Interrupt Enable 27. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
26CFIE26R/W0hCancellation Finished Interrupt Enable 26. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
25CFIE25R/W0hCancellation Finished Interrupt Enable 25. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
24CFIE24R/W0hCancellation Finished Interrupt Enable 24. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
23CFIE23R/W0hCancellation Finished Interrupt Enable 23. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
22CFIE22R/W0hCancellation Finished Interrupt Enable 22. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
21CFIE21R/W0hCancellation Finished Interrupt Enable 21. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
20CFIE20R/W0hCancellation Finished Interrupt Enable 20. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
19CFIE19R/W0hCancellation Finished Interrupt Enable 19. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
18CFIE18R/W0hCancellation Finished Interrupt Enable 18. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
17CFIE17R/W0hCancellation Finished Interrupt Enable 17. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
16CFIE16R/W0hCancellation Finished Interrupt Enable 16. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
15CFIE15R/W0hCancellation Finished Interrupt Enable 15. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
14CFIE14R/W0hCancellation Finished Interrupt Enable 14. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
13CFIE13R/W0hCancellation Finished Interrupt Enable 13. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
12CFIE12R/W0hCancellation Finished Interrupt Enable 12. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
11CFIE11R/W0hCancellation Finished Interrupt Enable 11. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
10CFIE10R/W0hCancellation Finished Interrupt Enable 10. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
9CFIE9R/W0hCancellation Finished Interrupt Enable 9. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
8CFIE8R/W0hCancellation Finished Interrupt Enable 8. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
7CFIE7R/W0hCancellation Finished Interrupt Enable 7. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
6CFIE6R/W0hCancellation Finished Interrupt Enable 6. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
5CFIE5R/W0hCancellation Finished Interrupt Enable 5. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
4CFIE4R/W0hCancellation Finished Interrupt Enable 4. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
3CFIE3R/W0hCancellation Finished Interrupt Enable 3. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
2CFIE2R/W0hCancellation Finished Interrupt Enable 2. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
1CFIE1R/W0hCancellation Finished Interrupt Enable 1. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled
0CFIE0R/W0hCancellation Finished Interrupt Enable 0. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled

25.7.44 TXEFC Register (Offset = F0h) [Reset = 00000000h]

TXEFC is shown in Table 25-55.

Return to the Summary Table.

DCAN Tx Event FIFO Configuration

Table 25-55 TXEFC Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-24EFWMR/WQ0hEvent FIFO Watermark 0 Watermark interrupt disabled 1-32 Level for Tx Event FIFO watermark interrupt (IR.TEFW) >32 Watermark interrupt disabled
23-22RESERVEDR0hReserved
21-16EFSR/WQ0hEvent FIFO Size. The Tx Event FIFO elements are indexed from 0 to EFS - 1. 0 Tx Event FIFO disabled 1-32 Number of Tx Event FIFO elements >32 Values greater than 32 are interpreted as 32
15-2EFSAR/WQ0hEvent FIFO Start Address. Start address of Tx Event FIFO in Message RAM (32-bit word address).
1-0RESERVEDR0hReserved

25.7.45 TXEFS Register (Offset = F4h) [Reset = 00000000h]

TXEFS is shown in Table 25-56.

Return to the Summary Table.

DCAN Tx Event FIFO Status

Table 25-56 TXEFS Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25TEFLR0hTx Event FIFO Element Lost. This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. 0 No Tx Event FIFO element lost 1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.
24EFFR0hEvent FIFO Full 0 Tx Event FIFO not full 1 Tx Event FIFO full
23-21RESERVEDR0hReserved
20-16EFPIR0hEvent FIFO Put Index.Tx Event FIFO write index pointer, range 0 to 31.
15-13RESERVEDR0hReserved
12-8EFGIR0hEvent FIFO Get Index. Tx Event FIFO read index pointer, range 0 to 31.
7-6RESERVEDR0hReserved
5-0EFFLR0hEvent FIFO Fill Level. Number of elements stored in Tx Event FIFO, range 0 to 32.

25.7.46 TXEFA Register (Offset = F8h) [Reset = 00000000h]

TXEFA is shown in Table 25-57.

Return to the Summary Table.

DCAN Tx Event FIFO Acknowledge

Table 25-57 TXEFA Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4-0EFAIR/W0hEvent FIFO Acknowledge Index. After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL.

25.7.47 SSPID Register (Offset = 200h) [Reset = 68E04901h]

SSPID is shown in Table 25-58.

Return to the Summary Table.

DCAN Subsystem Revision Register

Table 25-58 SSPID Register Field Descriptions
BitFieldTypeResetDescription
31-30SCHEMER1hPID Register Scheme
29-28BUR2hBusiness Unit: 0x2 = Processors
27-16MODULEIDR8E0hModule Identification Number
15-11RTLR9hRTL revision. Will vary depending on release
10-8MAJORR1hMajor Revision of the DCAN Subsystem
7-6CUSTOMR0hCustom Value
5-0MINORR1hMinor Revision of the DCAN Subsystem

25.7.48 SSCTL Register (Offset = 204h) [Reset = 00000008h]

SSCTL is shown in Table 25-59.

Return to the Summary Table.

DCAN Subsystem Control Register

Table 25-59 SSCTL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6EXTTSCNTENR/W0hExternal Timestamp Counter Enable. 0 External timestamp counter disabled 1 External timestamp counter enabled
5AUTOWUR/W0hAutomatic Wakeup Enable. Enables the DCANSS to automatically clear the DCAN CCCR.INIT bit, fully waking the DCAN up, on an enabled wakeup request. 0 Disable the automatic write to CCCR.INIT 1 Enable the automatic write to CCCR.INIT
4WUREQENR/W0hWakeup Request Enable. Enables the DCANSS to wakeup on CAN RXD activity. 0 Disable wakeup request 1 Enables wakeup request
3DBGSFR/W1hDebug Suspend Free Bit. Enables debug suspend. 0 Disable debug suspend 1 Enable debug suspend
2-0RESERVEDR0hReserved

25.7.49 SSSTA Register (Offset = 208h) [Reset = 0000000Xh]

SSSTA is shown in Table 25-60.

Return to the Summary Table.

DCAN Subsystem Status Register

Table 25-60 SSSTA Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2ENFDOERXhFlexible Datarate Operation Enable. Determines whether CAN FD operation may be enabled via the DCAN core CCCR.FDOE bit (bit 8) or if only standard CAN operation is possible with this instance of the DCAN. 0 DCAN is only capable of standard CAN communication 1 DCAN may be configured to perform CAN FD communication
1MEMINITSTAR0hMemory Initialization Done. 0 Message RAM initialization is in progress 1 Message RAM is initialized for use
0RESETR0hSoft Reset Status. 0 Not in reset 1 Reset is in progress

25.7.50 SSICS Register (Offset = 20Ch) [Reset = 00000000h]

SSICS is shown in Table 25-61.

Return to the Summary Table.

DCAN Subsystem Interrupt Clear Shadow Register

Table 25-61 SSICS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0TSCNTOVFLR-0/W1C0hExternal Timestamp Counter Overflow Interrupt Status Clear. Reads always return a 0. 0 Write of '0' has no effect 1 Write of '1' clears the DCANSS IRS.EXT_TS_CNTR_OVFL bit

25.7.51 SSIRS Register (Offset = 210h) [Reset = 00000000h]

SSIRS is shown in Table 25-62.

Return to the Summary Table.

DCAN Subsystem Interrupt Raw Status Register

Table 25-62 SSIRS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0TSCNTOVFLR/W1S0hExternal Timestamp Counter Overflow Interrupt Status. This bit is set by HW or by a SW write of '1'. To clear, use the ICS.EXT_TS_CNTR_OVFL bit. 0 External timestamp counter has not overflowed 1 External timestamp counter has overflowed When this bit is set to '1' by HW or SW, the EXT_TS_UNSERVICED_INTR_CNTR.EXT_TS_INTR_CNTR bit field will increment by 1.

25.7.52 SSIECS Register (Offset = 214h) [Reset = 00000000h]

SSIECS is shown in Table 25-63.

Return to the Summary Table.

DCAN Subsystem Interrupt Enable Clear Shadow Register

Table 25-63 SSIECS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0TSCNTOVFLR-0/W1C0hExternal Timestamp Counter Overflow Interrupt Enable Clear. Reads always return a 0. 0 Write of '0' has no effect 1 Write of '1' clears the DCANSS_IES.EXT_TS_CNTR_OVFL bit

25.7.53 SSIE Register (Offset = 218h) [Reset = 00000000h]

SSIE is shown in Table 25-64.

Return to the Summary Table.

DCAN Subsystem Interrupt Enable Register

Table 25-64 SSIE Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0TSCNTOVFLR/W1S0hExternal Timestamp Counter Overflow Interrupt Enable. A write of '0' has no effect. A write of '1' sets the IES.EXT_TS_CNTR_OVFL bit.

25.7.54 SSIES Register (Offset = 21Ch) [Reset = 00000000h]

SSIES is shown in Table 25-65.

Return to the Summary Table.

DCAN Subsystem Masked Interrupt Status. It is the logical AND of IRS and IE for the respective bits.

Table 25-65 SSIES Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0TSCNTOVFLR0hExternal Timestamp Counter Overflow masked interrupt status. 0 External timestamp counter overflow interrupt is cleared 1 External timestamp counter overflow interrupt is set

25.7.55 SSEOI Register (Offset = 220h) [Reset = 00000000h]

SSEOI is shown in Table 25-66.

Return to the Summary Table.

DCAN Subsystem End of Interrupt

Table 25-66 SSEOI Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0EOIR-0/W1S0hEnd of Interrupt. A write to this register will clear the associated interrupt. If the unserviced interrupt counter is > 1, another interrupt is generated. 0x00 External TS Interrupt is cleared 0x01 DCAN(0) interrupt is cleared 0x02 DCAN(1) interrupt is cleared Other writes are ignored.

25.7.56 EXTTSPS Register (Offset = 224h) [Reset = 00000000h]

EXTTSPS is shown in Table 25-67.

Return to the Summary Table.

DCAN Subsystem External Timestamp Prescaler 0

Table 25-67 EXTTSPS Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-0PRESCALERR/W0hExternal Timestamp Prescaler Reload Value. The external timestamp count rate is the host (system) clock rate divided by this value, except in the case of 0. A zero value in this bit field will act identically to a value of 0x000001.

25.7.57 EXTTSUSI Register (Offset = 228h) [Reset = 00000000h]

EXTTSUSI is shown in Table 25-68.

Return to the Summary Table.

DCAN Subsystem External Timestamp Unserviced Interrupts Counter

Table 25-68 EXTTSUSI Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4-0INTRCNTR0hExternal Timestamp Counter Unserviced Rollover Interrupts. If this value is > 1, an EOI write of '1' to bit 0 will issue another interrupt. The status of this bit field is affected by the DCANSS_IRS.EXT_TS_CNTR_OVFL bit field.

25.7.58 ERRREV Register (Offset = 400h) [Reset = 66A0EA00h]

ERRREV is shown in Table 25-69.

Return to the Summary Table.

DCAN error Aggregator Revision Register

Table 25-69 ERRREV Register Field Descriptions
BitFieldTypeResetDescription
31-30SCHEMER1hPID Register Scheme
29-28BUR2hBusiness Unit: 0x2 = Processors
27-16MODULEIDR6A0hModule Identification Number
15-11REVRTLR1DhRTL revision. Will vary depending on release
10-8REVMAJR2hMajor Revision of the Error Aggregator
7-6REVCUSTOMR0hCustom Revision of the Error Aggregator
5-0REVMINR0hMinor Revision of the Error Aggregator

25.7.59 ERRVEC Register (Offset = 408h) [Reset = 00000000h]

ERRVEC is shown in Table 25-70.

Return to the Summary Table.

Each error detection and correction (EDC) controller has a bank of error registers (offsets 0x10 - 0x3B) associated with it. These registers are accessed via an internal serial bus (SVBUS). To access them through the ECC aggregator the controller ID desired must be written to the ECC_VECTOR field, together with the RD_SVBUS trigger and RD_SVBUS_ADDRESS bit field. This initiates the serial read which consummates by setting the RD_SVBUS_DONE bit. At this point the addressed register may be read by a normal CPU read of the appropriate offset address.

Table 25-70 ERRVEC Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24SVBUSDONER0hRead Completion Flag
23-16RDSVBUSAR/W0hRead Address Offset
15RDSVBUSR-0/W1S0hRead Trigger
14-11RESERVEDR0hReserved
10-0ECCVECR/W0hECC RAM ID. Each error detection and correction (EDC) controller has a bank of error registers (offsets 0x10 - 0x3B) associated with it. These registers are accessed via an internal serial bus (SVBUS). To access them through the ECC aggregator the controller ID desired must be written to the ECC_VECTOR field, together with the RD_SVBUS trigger and RD_SVBUS_ADDRESS bit field. This initiates the serial read which consummates by setting the RD_SVBUS_DONE bit. At this point the addressed register may be read by a normal CPU read of the appropriate offset address. 0x000 Message RAM ECC controller is selected Others Reserved (do not use) Subsequent writes through the SVBUS (offsets 0x10 - 0x3B) have a delayed completion. To avoid conflicts, perform a read back of a register within this range after writing.

25.7.60 ERRSTA Register (Offset = 40Ch) [Reset = 00000002h]

ERRSTA is shown in Table 25-71.

Return to the Summary Table.

DCAN error Misc Status

Table 25-71 ERRSTA Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10-0NUMRAMSR2hNumber of RAMs. Number of ECC RAMs serviced by the aggregator.

25.7.61 ERRWRAPREV Register (Offset = 410h) [Reset = 66A46A02h]

ERRWRAPREV is shown in Table 25-72.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the DCANECC Vector Register.

Table 25-72 ERRWRAPREV Register Field Descriptions
BitFieldTypeResetDescription
31-30SCHEMER1hPID Register Scheme
29-28BUR2hBusiness Unit: 0x2 = Processors
27-16MODULEIDR6A4hModule Identification Number
15-11REVRTLRDhRTL revision. Will vary depending on release
10-8REVMAJR2hMajor Revision of the Error Aggregator
7-6REVCUSTOMR0hCustom Revision of the Error Aggregator
5-0REVMINR2hMinor Revision of the Error Aggregator

25.7.62 ERRCTL Register (Offset = 414h) [Reset = 00000187h]

ERRCTL is shown in Table 25-73.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the DCANECC Vector Register.

Table 25-73 ERRCTL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8CHECKSVBTOR/W1hEnables Serial VBUS timeout mechanism
7CHECKPARR/W1hEnables parity checking on internal data
6ERRONCER/W0hIf this bit is set, the FORCE_SEC/FORCE_DED will inject an error to the specified row only once. The FORCE_SEC bit will be cleared once a writeback happens. If writeback is not enabled, this error will be cleared the cycle following the read when the data is corrected. For double-bit errors, the FORCE_DED bit will be cleared the cycle following the double-bit error. Any subsequent reads will not force an error.
5FRCNROWR/W0hEnable single/double-bit error on the next RAM read, regardless of the MCANERR_ERR_CTRL1.ECC_ROW setting. For write through mode, this applies to writes as well as reads.
4FRCDEDR/W0hForce double-bit error. Cleared the cycle following the error if ERROR_ONCE is asserted. For write through mode, this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit.
3FRCSECR/W0hForce single-bit error. Cleared on a writeback or the cycle following the error if ERROR_ONCE is asserted. For write through mode, this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit.
2ENRMWR/W1hEnable read-modify-write on partial word writes
1ECCCHECKR/W1hEnable ECC Check. ECC is completely bypassed if both ECC_ENABLE and ECC_CHECK are '0'.
0ECCENR/W1hEnable ECC Generation

25.7.63 ERRCTL1 Register (Offset = 418h) [Reset = 00000000h]

ERRCTL1 is shown in Table 25-74.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the DCANECC Vector Register.

Table 25-74 ERRCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-0ECCROWR/W0hRow address where FORCE_SEC or FORCE_DED needs to be applied. This is ignored if FORCE_N_ROW is set.

25.7.64 ERRCTL2 Register (Offset = 41Ch) [Reset = 00000000h]

ERRCTL2 is shown in Table 25-75.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the DCANECC Vector Register.

Table 25-75 ERRCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-16ECCB2R/W0hSecond column/data bit that needs to be flipped when FORCE_DED is set
15-0ECCB1R/W0hColumn/Data bit that needs to be flipped when FORCE_SEC or FORCE_DED is set

25.7.65 ERRSTA1 Register (Offset = 420h) [Reset = 00000000h]

ERRSTA1 is shown in Table 25-76.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the DCANECC Vector Register.

Table 25-76 ERRSTA1 Register Field Descriptions
BitFieldTypeResetDescription
31-16ECCB1R0hECC Error Bit Position. Indicates the bit position in the RAM data that is in error on an SEC error. Only valid on an SEC error. 0 Bit 0 is in error 1 Bit 1 is in error 2 Bit 2 is in error 3 Bit 3 is in error ... 31 Bit 31 is in error >32 Invalid
15CLRCTLERRR/W1S0hWriting a '1' clears the CTRL_REG_ERROR bit
14-13CLRPARERRR/WD0hClear Parity Error. A write of a non-zero value to this bit field decrements the PARITY_ERROR bit field by the value provided.
12CLRECCOTR/W1C0hWriting a '1' clears the ECC_OTHER bit.
11-10CLRECCDEDR/WD0hClear ECC_DED. A write of a non-zero value to this bit field decrements the ECC_DED bit field by the value provided.
9-8CLRECCSECR/WD0hClear ECC_SEC. A write of a non-zero value to this bit field decrements the ECC_SEC bit field by the value provided.
7CTLERRR/W1S0hControl Register Error. A bit field in the control register is in an ambiguous state. This means that the redundancy registers have detected a state where not all values are the same and has defaulted to the reset state. S/W needs to re-write these registers to a known state. A write of 1 will set this interrupt flag.
6-5PARERRR/WI0hParity Error Status. A 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0 No parity error detected 1 One parity error was detected 2 Two parity errors were detected 3 Three parity errors were detected A write of a non-zero value to this bit field increments it by the value provided.
4ECCOTHERR/W1S0hSEC While Writeback Error Status 0 No SEC error while writeback pending 1 Indicates that successive single-bit errors have occurred while a writeback is still pending
3-2ECCDEDR/WI0hDouble Bit Error Detected Status. A 2-bit saturating counter of the number of DED errors that have occurred since last cleared. 0 No double-bit error detected 1 One double-bit error was detected 2 Two double-bit errors were detected 3 Three double-bit errors were detected A write of a non-zero value to this bit field increments it by the value provided.
1-0ECCSECR/WI0hSingle Bit Error Corrected Status. A 2-bit saturating counter of the number of SEC errors that have occurred since last cleared. 0 No single-bit error detected 1 One single-bit error was detected and corrected 2 Two single-bit errors were detected and corrected 3 Three single-bit errors were detected and corrected A write of a non-zero value to this bit field increments it by the value provided.

25.7.66 ERRSTA2 Register (Offset = 424h) [Reset = 00000000h]

ERRSTA2 is shown in Table 25-77.

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This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the DCANECC Vector Register.

Table 25-77 ERRSTA2 Register Field Descriptions
BitFieldTypeResetDescription
31-0ECCROWR0hIndicates the row address where the single or double-bit error occurred. This value is address offset/4.

25.7.67 ERRSTA3 Register (Offset = 428h) [Reset = 00000000h]

ERRSTA3 is shown in Table 25-78.

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This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the DCANECC Vector Register.

Table 25-78 ERRSTA3 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9CLRSVBTOR-0/W1C0hWrite 1 to clear the Serial VBUS Timeout Flag
8-2RESERVEDR0hReserved
1SVBUSTOR-0/W1S0hSerial VBUS Timeout Flag. Write 1 to set.
0WBPENDR0hDelayed Write Back Pending Status 0 No write back pending 1 An ECC data correction write back is pending

25.7.68 SECEOI Register (Offset = 43Ch) [Reset = 00000000h]

SECEOI is shown in Table 25-79.

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DCAN Single Error Corrected End of Interrupt Register

Table 25-79 SECEOI Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0EOIWRR-0/W1S0hWrite to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. Note that a write to the MCANERR_ERR_STAT1.CLR_ECC_SEC goes through the SVBUS and has a delayed completion. To avoid an additional interrupt, read the MCANERR_ERR_STAT1 register back prior to writing to this bit field.

25.7.69 SECSTA Register (Offset = 440h) [Reset = 00000000h]

SECSTA is shown in Table 25-80.

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DCANSingle Error Corrected Interrupt Status Register

Table 25-80 SECSTA Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0MGSPENDR-0/W1S0hMessage RAM SEC Interrupt Pending 0 No SEC interrupt is pending 1 SEC interrupt is pending

25.7.70 SECENSET Register (Offset = 480h) [Reset = 00000000h]

SECENSET is shown in Table 25-81.

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DCANSingle Error Corrected Interrupt Enable Set Register

Table 25-81 SECENSET Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0MSGENSETR/W1S0hMessage RAM SEC Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value.

25.7.71 SECENCLR Register (Offset = 4C0h) [Reset = 00000000h]

SECENCLR is shown in Table 25-82.

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DCANSingle Error Corrected Interrupt Enable Clear Register

Table 25-82 SECENCLR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0MSGENCLRR/W1C0hMessage RAM SEC Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value.

25.7.72 DEDEOI Register (Offset = 53Ch) [Reset = 00000000h]

DEDEOI is shown in Table 25-83.

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DCANDouble Error Detected End of Interrupt Register

Table 25-83 DEDEOI Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0EOIWRR-0/W1S0hWrite to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. Note that a write to the MCANERR_ERR_STAT1.CLR_ECC_DED goes through the SVBUS and has a delayed completion. To avoid an additional interrupt, read the MCANERR_ERR_STAT1 register back prior to writing to this bit field.

25.7.73 DEDSTA Register (Offset = 540h) [Reset = 00000000h]

DEDSTA is shown in Table 25-84.

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DCANDouble Error Detected Interrupt Status Register

Table 25-84 DEDSTA Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1TXREQPENDR-0/W1S0hTX Empty DMA Request Parity Interrupt Pending 0 No parity error interrupt is pending 1 A parity error interrupt is pending
0MSGPENDR-0/W1S0hMessage RAM DED Interrupt Pending 0 No DED interrupt is pending 1 DED interrupt is pending

25.7.74 DEDENSET Register (Offset = 580h) [Reset = 00000000h]

DEDENSET is shown in Table 25-85.

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DCANDouble Error Detected Interrupt Enable Set Register

Table 25-85 DEDENSET Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1TXREQENSETR/W1S0hTX Empty DMA Request Parity Interrupt Pending Enable Set. Writing a 1 to this bit enables the TX empty DMA request parity error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value.
0MSGENSETR/W1S0hMessage RAM DED Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value.

25.7.75 DEDENCLR Register (Offset = 5C0h) [Reset = 00000000h]

DEDENCLR is shown in Table 25-86.

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DCANDouble Error Detected Interrupt Enable Clear Register

Table 25-86 DEDENCLR Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1TXREQENCLRR/W1C0hTX Empty DMA Request Parity Interrupt Pending Enable Clear. Writing a 1 to this bit disables the TX empty DMA request parity error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value.
0MSGENCLRR/W1C0hMessage RAM DED Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value.

25.7.76 AGGRENSET Register (Offset = 600h) [Reset = 00000000h]

AGGRENSET is shown in Table 25-87.

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DCAN error Aggregator Enable Set Register

Table 25-87 AGGRENSET Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1TIMEOUTR/W1S0hWrite 1 to enable timeout errors. Reads return the corresponding enable bit's current value.
0PARITYR/W1S0hWrite 1 to enable parity errors. Reads return the corresponding enable bit's current value.

25.7.77 AGGRENCLR Register (Offset = 604h) [Reset = 00000000h]

AGGRENCLR is shown in Table 25-88.

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DCAN error Aggregator Enable Clear Register

Table 25-88 AGGRENCLR Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1TIMEOUTR/W1C0hWrite 1 to disable timeout errors. Reads return the corresponding enable bit's current value.
0PARITYR/W1C0hWrite 1 to disable parity errors. Reads return the corresponding enable bit's current value.

25.7.78 AGGRSTASET Register (Offset = 608h) [Reset = 00000000h]

AGGRSTASET is shown in Table 25-89.

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DCAN error Aggregator Status Set Register

Table 25-89 AGGRSTASET Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-2TIMEOUTR/WI0hAggregator Serial VBUS Timeout Error Status 2-bit saturating counter of the number of SVBUS timeout errors that have occurred since last cleared. 0 No timeout errors have occurred 1 One timeout error has occurred 2 Two timeout errors have occurred 3 Three timeout errors have occurred A write of a non-zero value to this bit field increments it by the value provided.
1-0PARITYR/WI0hAggregator Parity Error Status 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0 No parity errors have occurred 1 One parity error has occurred 2 Two parity errors have occurred 3 Three parity errors have occurred A write of a non-zero value to this bit field increments it by the value provided.

25.7.79 AGGRSTACLR Register (Offset = 60Ch) [Reset = 00000000h]

AGGRSTACLR is shown in Table 25-90.

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DCAN error Aggregator Status Clear Register

Table 25-90 AGGRSTACLR Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-2TIMEOUTR/WD0hAggregator Serial VBUS Timeout Error Status 2-bit saturating counter of the number of SVBUS timeout errors that have occurred since last cleared. 0 No timeout errors have occurred 1 One timeout error has occurred 2 Two timeout errors have occurred 3 Three timeout errors have occurred A write of a non-zero value to this bit field decrements it by the value provided.
1-0PARITYR/WD0hAggregator Parity Error Status 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0 No parity errors have occurred 1 One parity error has occurred 2 Two parity errors have occurred 3 Three parity errors have occurred A write of a non-zero value to this bit field decrements it by the value provided.

25.7.80 DESC Register (Offset = 800h) [Reset = 00000000h]

DESC is shown in Table 25-91.

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This register identifies the peripheral and its exact version.

Table 25-91 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR940hModule identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
  • 0h = Smallest value
  • FFFFh = Highest possible value
15-12FEATUREVERR0hFeature Set for the module *instance*
  • 0h = DCANmodule with CAN-FD mode enabled <<Internal Note: This is an in-IP paper spin variant. How does this map to the SYS_MCAN_ENABLE_FD choice value?>>
  • 1h = DCANmodule with CAN-FD mode disabled <<Internal Note: This is an in-IP paper spin variant. How does this map to the SYS_MCAN_ENABLE_FD choice value?>>
11-8RESERVEDR0hReserved
7-4MAJREVR0hMajor rev of the IP
  • 0h = Smallest value
  • Fh = Highest possible value
3-0MINREVR0hMinor rev of the IP
  • 0h = Smallest value
  • Fh = Highest possible value

25.7.81 IMASK0 Register (Offset = 844h) [Reset = 00000000h]

IMASK0 is shown in Table 25-92.

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Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Table 25-92 IMASK0 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7DMADONE1R/W0hMask Channel1 Event.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
6DMADONE0R/W0hMask Channel1 Event.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
5FE2R/W0hMask Channel1 Event.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
4TSORWAKER/W0hMask Channel1 Event.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
3DEDR/W0hMask Channel1 Event.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
2SECR/W0hMask Channel1 Event.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
1INTL1R/W0hMask Channel1 Event.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
0INTL0R/W0hMask channel0 Event
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask

25.7.82 RIS0 Register (Offset = 848h) [Reset = 00000000h]

RIS0 is shown in Table 25-93.

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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS0 register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Table 25-93 RIS0 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7DMADONE1R0hRaw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
6DMADONE0R0hRaw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
5FE2R0hRaw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
4TSORWAKER0hRaw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
3DEDR0hRaw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
2SECR0hRaw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
1INTL1R0hRaw interrupt status for EVENT1. This bit is set to 1 when an event is received on EVENT1 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when the captured time value is read from the CH1CAPT register.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
0INTL0R0hRaw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured

25.7.83 MIS0 Register (Offset = 84Ch) [Reset = 00000000h]

MIS0 is shown in Table 25-94.

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Masked interrupt status. This is an AND of the IMASK and RIS registers.

Table 25-94 MIS0 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7DMADONE1R0hMask interrupt status for EVENT0
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
6DMADONE0R0hMask interrupt status for EVENT0
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
5FE2R0hMask interrupt status for EVENT0
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
4TSORWAKER0hMask interrupt status for EVENT0
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
3DEDR0hMask interrupt status for EVENT0
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
2SECR0hMask interrupt status for EVENT0
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
1INTL1R0hMask interrupt status for EVENT1
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
0INTL0R0hMask interrupt status for EVENT0
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured

25.7.84 ISET0 Register (Offset = 850h) [Reset = 00000000h]

ISET0 is shown in Table 25-95.

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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET0 will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Table 25-95 ISET0 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7DMADONE1W0hSets EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Sets interrupt
6DMADONE0W0hSets EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Sets interrupt
5FE2W0hSets EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Sets interrupt
4TSORWAKEW0hSets EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Sets interrupt
3DEDW0hSets EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Sets interrupt
2SECW0hSets EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Sets interrupt
1INTL1W0hSets EVENT1 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Sets interrupt
0INTL0W0hSets EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Sets interrupt

25.7.85 ICLR0 Register (Offset = 854h) [Reset = 00000000h]

ICLR0 is shown in Table 25-96.

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Interrupt clear. Write a 1 to clear corresponding Interrupt.

Table 25-96 ICLR0 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7DMADONE1W0hClears EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clears the Event
6DMADONE0W0hClears EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clears the Event
5FE2W0hClears EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clears the Event
4TSORWAKEW0hClears EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clears the Event
3DEDW0hClears EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clears the Event
2SECW0hClears EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clears the Event
1INTL1W0hClears EVENT1 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clears the Event
0INTL0W0hClears EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clears the Event

25.7.86 IMASK1 Register (Offset = 868h) [Reset = 00000000h]

IMASK1 is shown in Table 25-97.

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Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Table 25-97 IMASK1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7DMADONE1R/W0hMask Channel1 Event.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
6DMADONE0R/W0hMask Channel1 Event.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
5FE2R/W0hMask Channel1 Event.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
4TSORWAKER/W0hMask Channel1 Event.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
3DEDR/W0hMask Channel1 Event.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
2SECR/W0hMask Channel1 Event.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
1INTL1R/W0hMask Channel1 Event.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
0INTL0R/W0hMask channel0 Event
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask

25.7.87 RIS1 Register (Offset = 86Ch) [Reset = 00000000h]

RIS1 is shown in Table 25-98.

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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS0 register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Table 25-98 RIS1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7DMADONE1R0hRaw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
6DMADONE0R0hRaw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
5FE2R0hRaw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
4TSORWAKER0hRaw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
3DEDR0hRaw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
2SECR0hRaw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
1INTL1R0hRaw interrupt status for EVENT1. This bit is set to 1 when an event is received on EVENT1 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when the captured time value is read from the CH1CAPT register.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
0INTL0R0hRaw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured

25.7.88 MIS1 Register (Offset = 870h) [Reset = 00000000h]

MIS1 is shown in Table 25-99.

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Masked interrupt status. This is an AND of the IMASK and RIS registers.

Table 25-99 MIS1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7DMADONE1R0hMask interrupt status for EVENT0
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
6DMADONE0R0hMask interrupt status for EVENT0
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
5FE2R0hMask interrupt status for EVENT0
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
4TSORWAKER0hMask interrupt status for EVENT0
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
3DEDR0hMask interrupt status for EVENT0
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
2SECR0hMask interrupt status for EVENT0
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
1INTL1R0hMask interrupt status for EVENT1
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
0INTL0R0hMask interrupt status for EVENT0
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured

25.7.89 ISET1 Register (Offset = 874h) [Reset = 00000000h]

ISET1 is shown in Table 25-100.

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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET0 will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Table 25-100 ISET1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7DMADONE1W0hSets EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Sets interrupt
6DMADONE0W0hSets EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Sets interrupt
5FE2W0hSets EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Sets interrupt
4TSORWAKEW0hSets EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Sets interrupt
3DEDW0hSets EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Sets interrupt
2SECW0hSets EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Sets interrupt
1INTL1W0hSets EVENT1 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Sets interrupt
0INTL0W0hSets EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Sets interrupt

25.7.90 ICLR1 Register (Offset = 878h) [Reset = 00000000h]

ICLR1 is shown in Table 25-101.

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Interrupt clear. Write a 1 to clear corresponding Interrupt.

Table 25-101 ICLR1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7DMADONE1W0hClears EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clears the Event
6DMADONE0W0hClears EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clears the Event
5FE2W0hClears EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clears the Event
4TSORWAKEW0hClears EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clears the Event
3DEDW0hClears EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clears the Event
2SECW0hClears EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clears the Event
1INTL1W0hClears EVENT1 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clears the Event
0INTL0W0hClears EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clears the Event

25.7.91 CLKDIV Register (Offset = 904h) [Reset = 00000000h]

CLKDIV is shown in Table 25-102.

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Needs to go to the Management aperture once available

Table 25-102 CLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0RATIOR/W0hClock divide ratio specification. Enables configuring clock divide settings for the DCANfunctional clock input to the MCAN-SS.
  • 0h (R/W) = Divides input clock by 1
  • 1h (R/W) = Divides input clock by 2
  • 2h (R/W) = Divides input clock by 4

25.7.92 CLKCTL Register (Offset = 908h) [Reset = 00000000h]

CLKCTL is shown in Table 25-103.

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DCANSS clock stop control MMR. <Internal note> Bus clock for the Dragon wrapper MMRs (including this MMR) is not gated by this register.

Table 25-103 CLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8WUGLTFLTENR/W0hSetting this bit enables the glitch filter on DCAN RXD input, which wakes up the DCANcontroller to exit clock gating.
  • 0h = Disable glitch filter enable on RXD input when DCANis in clock stop mode (waiting for event on RXD input for clock stop wakeup).
  • 1h = Enable glitch filter enable on RXD input when DCANis in clock stop mode (waiting for event on RXD input for clock stop wakeup).
7-5RESERVEDR0hReserved
4WUINTENR/W0hThis bit controls enabling or disabling the DCANIP clock stop wakeup interrupt (when CTRL.WAKEUPREQEN wakeup request is enabled to wakeup DCANIP upon CAN RXD activity)
  • 0h = Disable DCANIP clock stop wakeup interrupt
  • 1h = Enable DCANIP clock stop wakeup interrupt
3-1RESERVEDR0hReserved
0STOPREQR/W0hThis bit is used to enable/disable DCANclock (both host clock and functional clock) gating request. Note: This bit can be reset by HW by Clock-Stop Wake-up via CAN RX Activity. See spec for more details.
  • 0h = Disable MCAN-SS clock stop request
  • 1h = Enable MCAN-SS clock stop request

25.7.93 CLKSTA Register (Offset = 90Ch) [Reset = 00000000h]

CLKSTA is shown in Table 25-104.

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DCANSS clock stop status register to indicate status of clock stop mechanism

Table 25-104 CLKSTA Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4STPREQHWOVR0hDCANSS clock stop HW override status bit. This bit indicates when the CLKCTL.STOPREQ bit has been cleared by HW when a clock-stop wake-up event via CAN RX activity is triggered.
  • 0h = CLKCTL.STOPREQ bit has not been cleared by HW.
  • 1h = CLKCTL.STOPREQ bit has been cleared by HW.
3-1RESERVEDR0hReserved
0STPACKSTAR0hClock stop acknowledge status from DCANIP
  • 0h = No clock stop acknowledged.
  • 1h = MCAN-SS may be clock gated by stopping both the CAN host and functional clocks.

25.7.94 DMA0CTL Register (Offset = 924h) [Reset = 00000000h]

DMA0CTL is shown in Table 25-105.

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DCANSS fixed DMA0 control and configuration register

Table 25-105 DMA0CTL Register Field Descriptions
BitFieldTypeResetDescription
31-27BUFTTOOFSTR/W0hIndicates the Rx-buffer (index x) to be mapped to FE_0 (FE001) and automatically maps and Rx buffer (index x+1) to FE_1 (FE010) Valid range: Rxbuffer (0) to Rxbuffer (30)
  • 0h = Minimum index value: 0
  • 1Eh = Maximum index value: 30 Note: RX_FE_TTO_SEL Rx buffer index selection for FE01 cannot be 31, as Rxbuffer (index +1) maps to 32, which requires updating NDAT1 and NDAT2 value, which is not supported.
26-25RESERVEDR0hReserved
24FEOTOSELR/W0hRX_FE_OTO_SEL is used to select the DCAN RX buffer filter event signal mapped to trigger fixed DCANSS DMA channel trigger
  • 0h = Filter Event 0
  • 1h = Filter Event 1
23-22RESERVEDR0hReserved
21-16BRPMTONUMR/W2hNumber of TX buffer request pending (BRP) signals for multi-to-one DMA trigger mapping sequence, starting from the buffer offset number selected by TX_BRP_MTO_OFFST bits
  • 2h = Min number for TX BRP multi-to-one DMA trigger mapping sequence is 2
  • 20h = Max number for TX BRP multi-to-one DMA trigger mapping sequence is 32
15RESERVEDR0hReserved
14-10BRPMTOOFSTR/W0hTX_BRP_MTO_OFFST selects the Tx buffer offset number for the multi-to-one round robin DMA trigger mode.
  • 0h = TX Buffer Request Pending 0
  • 1h = TX Buffer Request Pending 1
  • 2h = TX Buffer Request Pending 2
  • 3h = TX Buffer Request Pending 3
  • 4h = TX Buffer Request Pending 4
  • 5h = TX Buffer Request Pending 5
  • 6h = TX Buffer Request Pending 6
  • 7h = TX Buffer Request Pending 7
  • 8h = TX Buffer Request Pending 8
  • 9h = TX Buffer Request Pending 9
  • Ah = TX Buffer Request Pending 10
  • Bh = TX Buffer Request Pending 11
  • Ch = TX Buffer Request Pending 12
  • Dh = TX Buffer Request Pending 13
  • Eh = TX Buffer Request Pending 14
  • Fh = TX Buffer Request Pending 15
  • 10h = TX Buffer Request Pending 16
  • 11h = TX Buffer Request Pending 17
  • 12h = TX Buffer Request Pending 18
  • 13h = TX Buffer Request Pending 19
  • 14h = TX Buffer Request Pending 20
  • 15h = TX Buffer Request Pending 21
  • 16h = TX Buffer Request Pending 22
  • 17h = TX Buffer Request Pending 23
  • 18h = TX Buffer Request Pending 24
  • 19h = TX Buffer Request Pending 25
  • 1Ah = TX Buffer Request Pending 26
  • 1Bh = TX Buffer Request Pending 27
  • 1Ch = TX Buffer Request Pending 28
  • 1Dh = TX Buffer Request Pending 29
  • 1Eh = TX Buffer Request Pending 30
  • 1Fh = TX Buffer Request Pending 31
9RESERVEDR0hReserved
8-4BRPOTOSELR/W0hTX_BRP_OTO_SEL is used to select the DCAN TX buffer request pending (BRP) signal mapped to trigger fixed DCANSS DMA channel trigger
  • 0h = TX Buffer Request Pending 0
  • 1h = TX Buffer Request Pending 1
  • 2h = TX Buffer Request Pending 2
  • 3h = TX Buffer Request Pending 3
  • 4h = TX Buffer Request Pending 4
  • 5h = TX Buffer Request Pending 5
  • 6h = TX Buffer Request Pending 6
  • 7h = TX Buffer Request Pending 7
  • 8h = TX Buffer Request Pending 8
  • 9h = TX Buffer Request Pending 9
  • Ah = TX Buffer Request Pending 10
  • Bh = TX Buffer Request Pending 11
  • Ch = TX Buffer Request Pending 12
  • Dh = TX Buffer Request Pending 13
  • Eh = TX Buffer Request Pending 14
  • Fh = TX Buffer Request Pending 15
  • 10h = TX Buffer Request Pending 16
  • 11h = TX Buffer Request Pending 17
  • 12h = TX Buffer Request Pending 18
  • 13h = TX Buffer Request Pending 19
  • 14h = TX Buffer Request Pending 20
  • 15h = TX Buffer Request Pending 21
  • 16h = TX Buffer Request Pending 22
  • 17h = TX Buffer Request Pending 23
  • 18h = TX Buffer Request Pending 24
  • 19h = TX Buffer Request Pending 25
  • 1Ah = TX Buffer Request Pending 26
  • 1Bh = TX Buffer Request Pending 27
  • 1Ch = TX Buffer Request Pending 28
  • 1Dh = TX Buffer Request Pending 29
  • 1Eh = TX Buffer Request Pending 30
  • 1Fh = TX Buffer Request Pending 31
3-2TRIGSELR/W0hDMA trigger select bits used to select between DCAN TX one-to-one mapping, DCAN TX multi-to-one round robin mapping and DCAN Rx one-to-one mapping options
  • 0h = DCAN TX Buffer one-to-one Tx BRP (buffer request pending) trigger to DMA channel select
  • 1h = DCAN TX Buffer multi-to-one round robin, Tx BRP (buffer request pending) triggers to DMA channel select
  • 2h = DCAN RX Buffer one-to-one Tx BRP (buffer request pending) trigger to DMA channel select
  • 3h = Rx buffer two-to-one DMA trigger
1RESERVEDR0hReserved
0TRIGENR/W0hDMA_TRIG_EN is used to enable/disable DCAN RX, TX triggers to DCANSS fixed DMA channel. <Note to design> check if this bit is needed depending on if similar functionality is enabled in the EXT_DMA aperture.
  • 0h = DCANSS fixed DMA channel trigger is disabled.
  • 1h = DCANSS fixed DMA channel trigger is enabled.

25.7.95 DMA1CTL Register (Offset = 92Ch) [Reset = 00000000h]

DMA1CTL is shown in Table 25-106.

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DCANSS fixed DMA1 control and configuration register

Table 25-106 DMA1CTL Register Field Descriptions
BitFieldTypeResetDescription
31-27BUFTTOOFSTR/W0hIndicates the Rx-buffer (index x) to be mapped to FE_0 (FE001) and automatically maps and Rx buffer (index x+1) to FE_1 (FE010) Valid range: Rxbuffer (0) to Rxbuffer (30)
  • 0h = Minimum index value: 0
  • 1Eh = Maximum index value: 30 Note: RX_FE_TTO_SEL Rx buffer index selection for FE01 cannot be 31, as Rxbuffer (index +1) maps to 32, which requires updating NDAT1 and NDAT2 value, which is not supported.
26-25RESERVEDR0hReserved
24FEOTOSELR/W0hRX_FE_OTO_SEL is used to select the DCAN RX buffer filter event signal mapped to trigger fixed DCANSS DMA channel trigger
  • 0h = Filter Event 0
  • 1h = Filter Event 1
23-22RESERVEDR0hReserved
21-16BRPMTONUMR/W2hNumber of TX buffer request pending (BRP) signals for multi-to-one DMA trigger mapping sequence, starting from the buffer offset number selected by TX_BRP_MTO_OFFST bits
  • 2h = Min number for TX BRP multi-to-one DMA trigger mapping sequence is 2
  • 20h = Max number for TX BRP multi-to-one DMA trigger mapping sequence is 32
15RESERVEDR0hReserved
14-10BRPMTOOFSTR/W0hTX_BRP_MTO_OFFST selects the Tx buffer offset number for the multi-to-one round robin DMA trigger mode.
  • 0h = TX Buffer Request Pending 0
  • 1h = TX Buffer Request Pending 1
  • 2h = TX Buffer Request Pending 2
  • 3h = TX Buffer Request Pending 3
  • 4h = TX Buffer Request Pending 4
  • 5h = TX Buffer Request Pending 5
  • 6h = TX Buffer Request Pending 6
  • 7h = TX Buffer Request Pending 7
  • 8h = TX Buffer Request Pending 8
  • 9h = TX Buffer Request Pending 9
  • Ah = TX Buffer Request Pending 10
  • Bh = TX Buffer Request Pending 11
  • Ch = TX Buffer Request Pending 12
  • Dh = TX Buffer Request Pending 13
  • Eh = TX Buffer Request Pending 14
  • Fh = TX Buffer Request Pending 15
  • 10h = TX Buffer Request Pending 16
  • 11h = TX Buffer Request Pending 17
  • 12h = TX Buffer Request Pending 18
  • 13h = TX Buffer Request Pending 19
  • 14h = TX Buffer Request Pending 20
  • 15h = TX Buffer Request Pending 21
  • 16h = TX Buffer Request Pending 22
  • 17h = TX Buffer Request Pending 23
  • 18h = TX Buffer Request Pending 24
  • 19h = TX Buffer Request Pending 25
  • 1Ah = TX Buffer Request Pending 26
  • 1Bh = TX Buffer Request Pending 27
  • 1Ch = TX Buffer Request Pending 28
  • 1Dh = TX Buffer Request Pending 29
  • 1Eh = TX Buffer Request Pending 30
  • 1Fh = TX Buffer Request Pending 31
9RESERVEDR0hReserved
8-4BRPOTOSELR/W0hTX_BRP_OTO_SEL is used to select the DCAN TX buffer request pending (BRP) signal mapped to trigger fixed DCANSS DMA channel trigger
  • 0h = TX Buffer Request Pending 0
  • 1h = TX Buffer Request Pending 1
  • 2h = TX Buffer Request Pending 2
  • 3h = TX Buffer Request Pending 3
  • 4h = TX Buffer Request Pending 4
  • 5h = TX Buffer Request Pending 5
  • 6h = TX Buffer Request Pending 6
  • 7h = TX Buffer Request Pending 7
  • 8h = TX Buffer Request Pending 8
  • 9h = TX Buffer Request Pending 9
  • Ah = TX Buffer Request Pending 10
  • Bh = TX Buffer Request Pending 11
  • Ch = TX Buffer Request Pending 12
  • Dh = TX Buffer Request Pending 13
  • Eh = TX Buffer Request Pending 14
  • Fh = TX Buffer Request Pending 15
  • 10h = TX Buffer Request Pending 16
  • 11h = TX Buffer Request Pending 17
  • 12h = TX Buffer Request Pending 18
  • 13h = TX Buffer Request Pending 19
  • 14h = TX Buffer Request Pending 20
  • 15h = TX Buffer Request Pending 21
  • 16h = TX Buffer Request Pending 22
  • 17h = TX Buffer Request Pending 23
  • 18h = TX Buffer Request Pending 24
  • 19h = TX Buffer Request Pending 25
  • 1Ah = TX Buffer Request Pending 26
  • 1Bh = TX Buffer Request Pending 27
  • 1Ch = TX Buffer Request Pending 28
  • 1Dh = TX Buffer Request Pending 29
  • 1Eh = TX Buffer Request Pending 30
  • 1Fh = TX Buffer Request Pending 31
3-2TRIGSELR/W0hDMA trigger select bits used to select between DCAN TX one-to-one mapping, DCAN TX multi-to-one round robin mapping and DCAN Rx one-to-one mapping options
  • 0h = DCAN TX Buffer one-to-one Tx BRP (buffer request pending) trigger to DMA channel select
  • 1h = DCAN TX Buffer multi-to-one round robin Tx BRP (buffer request pending) triggers to DMA channel select
  • 2h = DCAN RX Buffer one-to-one Tx BRP (buffer request pending) trigger to DMA channel select
  • 3h = Rx buffer two-to-one DMA trigger
1RESERVEDR0hReserved
0TRIGENR/W0hDMA_TRIG_EN is used to enable/disable DCAN RX, TX triggers to DCANSS fixed DMA channel. <Note to design> check if this bit is needed depending on if similar functionality is enabled in the EXT_DMA aperture.
  • 0h = DCANSS fixed DMA channel trigger is disabled.
  • 1h = DCANSS fixed DMA channel trigger is enabled.

25.7.96 TTOFE0 Register (Offset = 938h) [Reset = 00000000h]

TTOFE0 is shown in Table 25-107.

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Rx buffer (index x) base address. <Internal: Absolute address within DCAN IP: 0x7938> Applicable to Rx buffer DMA two-to-one mode mapped to FE001 trigger: >> LS bits 0:1 in this MMR are reserved and read as '0' as the DCAN SRAM is 4 byte data addressable. >> Index x is selected using DMAn_CTL.RX_FE_TTO_SEL bits.

Table 25-107 TTOFE0 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hReserved
14-2BASEADDRR/W0hFE0 Rx Buf x Base address (14:2). Address should be computed based on the 14-bit RBSA (Rx buffer start address) + offset (depending on Rx buffer element index value and data length code (DLC) for all the buffer elements before the Rx buffer element (x))
  • 0h = Min address offset within DCANSS SRAM: 0x0
  • 1FFFh = Max address offset within DCANSS SRAM: 0x1fff
1-0RESERVEDR0hReserved

25.7.97 TTOFE1 Register (Offset = 948h) [Reset = 00000000h]

TTOFE1 is shown in Table 25-108.

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Rx buffer (index x+1) base address <Internal: Absolute address within DCAN IP: 0x7948> Applicable to Rx buffer DMA two-to-one mode mapped to FE010 trigger: >> LS bits 0:1 in this MMR are reserved and read as '0' as the DCAN SRAM is 4 byte data addressable. >> Index x is selected using DMAn_CTL.RX_FE_TTO_SEL bits.

Table 25-108 TTOFE1 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hReserved
14-2BASEADDRR/W0hFE010 Rx Buf x Base adddress (14:2). Address should be compited based on the 14-bit RBSA (Rx buffer start address) + offset (depending on Rx buffer element index value and data length code (DLC) for all the buffer elements before the Rx buffer element (x+1))
  • 0h = Min address offset within DCANSS SRAM: 0x0
  • 1FFFh = Max address offset within DCANSS SRAM: 0x1fff
1-0RESERVEDR0hReserved

25.7.98 TTONDAT1 Register (Offset = 950h) [Reset = 00000000h]

TTONDAT1 is shown in Table 25-109.

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Rx Buffer two-to-one DMA mode, hardware NDAT1 value register. The address of this register is programmed as the DMA source address register for moving NDAT1 value during DMA operation. This register is automatically updated on the fly depending on FE001/FE010 (Rxbuf(x)/Rxbuf(x+1)) ongoing transfer.

Table 25-109 TTONDAT1 Register Field Descriptions
BitFieldTypeResetDescription
31-0NDAT1VALR0hNDAT1 value to be programmed onto MCAN.NDAT1 MMR. Automatically updated by HW.
  • 0h = Min value = 0x0 (not bits set)
  • 80000000h = max value = (bit 31 set) = 0x80000000

25.7.99 CLKCFG Register (Offset = 2000h) [Reset = 00000000h]

CLKCFG is shown in Table 25-110.

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Clock Configuration MMR for **DCAN**

Table 25-110 CLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-5CLKSELR/W0hDCAN clock selection
  • 0h = No clock is selected
  • 1h = 80Mhz host clock is selected.
  • 2h = HFXT is selected as source
  • 3h = Un-swallowed clock 80Mhz is selected.
4RAMENR/W0hRam Enable Paper spin option.
3-1RESERVEDR0hReserved
0CLKENR/W0h0: **DCAN** clock disabled 1: **DCAN** clock enabled