SWRU626 December   2025 CC3501E , CC3551E

 

  1.   1
  2. 1 Read This First
    1. 1.1 About This Manual
    2. 1.2 Register, Field, and Bit Calls
    3.     Trademarks
  3. 2 Architecture Overview
    1. 2.1  Target Applications
    2. 2.2  Introduction
    3. 2.3  Internal System Diagram
    4. 2.4  Arm Cortex M33
      1. 2.4.1 Processor Core
      2. 2.4.2 SysTick Timer
      3. 2.4.3 Nested Vectored Interrupt Controller
      4. 2.4.4 System Control Block (SCB)
      5. 2.4.5 TI AI instruction extensions
    5. 2.5  Power Management
      1. 2.5.1 VDD_MAIN
      2. 2.5.2 VDD_IO
      3. 2.5.3 VDDSF
      4. 2.5.4 VDD_PA
    6. 2.6  Debug Subsystem (DEBUGSS)
    7. 2.7  Memory Subsystem (MEMSS)
      1. 2.7.1 External Memory Interface
    8. 2.8  Hardware Security Module
    9. 2.9  General Purpose Timers (GPT)
    10. 2.10 Real Time Clock (RTC)
    11. 2.11 Direct Memory Access
    12. 2.12 GPIOs
    13. 2.13 Communication Peripherals
      1. 2.13.1 UART
      2. 2.13.2 I2C
      3. 2.13.3 SPI
      4. 2.13.4 I2S
      5. 2.13.5 SDMMC
      6. 2.13.6 SDIO
      7. 2.13.7 CAN
      8. 2.13.8 ADC
  4. 3  Arm Cortex-M33 Processor
    1. 3.1 Arm Cortex-M33 Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 M33 instantiation parameters
    4. 3.4 Arm Cortex-M33 System Peripheral Details
      1. 3.4.1 Floating Point Unit (FPU)
      2. 3.4.2 Memory Protection Unit (MPU)
      3. 3.4.3 Digital Signal Processing (DSP)
      4. 3.4.4 Security Attribution Unit (SAU)
      5. 3.4.5 System Timer
      6. 3.4.6 Nested Vectored Interrupt Controller
      7. 3.4.7 System Control Block
      8. 3.4.8 System Control Space
    5. 3.5 CPU Sub-System Peripheral Details
      1. 3.5.1 Trace Port Interface Unit (TPIU)
      2. 3.5.2 DAP Bridge and Debug Authentication
      3. 3.5.3 Implementation Defined Attribution Unit (IDAU)
    6. 3.6 Programming Model
      1. 3.6.1 Modes of operation and execution
        1. 3.6.1.1 Security states
        2. 3.6.1.2 Operating modes
        3. 3.6.1.3 Operating states
        4. 3.6.1.4 Privileged access and unprivileged user access
      2. 3.6.2 Instruction set summary
      3. 3.6.3 Memory model
        1. 3.6.3.1 Private Peripheral Bus
        2. 3.6.3.2 Unaligned accesses
      4. 3.6.4 Processor core registers summary
      5. 3.6.5 Exceptions
        1. 3.6.5.1 Exception handling and prioritization
    7. 3.7 TrustZone-M
      1. 3.7.1 Overview
      2. 3.7.2 M33 Configuration
      3. 3.7.3 Description of elements
        1. 3.7.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 3.7.3.1.1 Expected use
    8. 3.8 CC35xx Host MCU Registers
      1. 3.8.1 HOSTMCU_AON Registers
      2. 3.8.2 HOST_MCU Registers
      3. 3.8.3 HOST_MCU_SEC Registers
    9. 3.9 Arm® Cortex®-M33 Registers
      1. 3.9.1  CPU_ROM_TABLE Registers
      2. 3.9.2  TPIU Registers
      3. 3.9.3  DCB Registers
      4. 3.9.4  DIB Registers
      5. 3.9.5  DWT Registers
      6. 3.9.6  FPB Registers
      7. 3.9.7  FPE Registers
      8. 3.9.8  ICB Registers
      9. 3.9.9  ITM Registers
      10. 3.9.10 MPU Registers
      11. 3.9.11 NVIC Registers
      12. 3.9.12 SAU Registers
      13. 3.9.13 SCB Registers
      14. 3.9.14 SYSTIMER Registers
      15. 3.9.15 SYSTICK Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation to HardFault
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Manager
      1. 5.4.1 Introduction
      2. 5.4.2 Interrupts List
      3. 5.4.3 Wakeup Sources
      4. 5.4.4 Shared Peripherals MUX Selector
        1. 5.4.4.1 ADC HW Event Selector Mux
        2. 5.4.4.2 I2S HW Event Selector Mux
        3. 5.4.4.3 PDM HW Event Selector Mux
      5. 5.4.5 Timers MUX Selector Mux
        1. 5.4.5.1 SysTimer0 HW Event Selector Mux
        2. 5.4.5.2 SysTimer1 HW Event Selector Mux
        3. 5.4.5.3 RTC HW Event Selector Mux
      6. 5.4.6 GPTIMERs MUX Selector Mux
        1. 5.4.6.1 GPTIMER0 HW Event Selector Mux
        2. 5.4.6.2 GPTIMER1 HW Event Selector Mux
    5. 5.5 SOC_IC Registers
    6. 5.6 SOC_AON Registers
    7. 5.7 SOC_AAON Registers
  7. 6 Debug Subsystem (DEBUGSS)
    1. 6.1 Introduction
    2. 6.2 Block Diagram
    3. 6.3 Overview
    4. 6.4 Physical Interface
    5. 6.5 Debug Access Ports
    6. 6.6 Debug Features
      1. 6.6.1 Processor Debug
      2. 6.6.2 Breakpoint Unit (BPU)
      3. 6.6.3 Peripheral Debug
    7. 6.7 Behavior in Low Power Modes
    8. 6.8 Debug Access Control
    9. 6.9 SOC_DEBUGSS Registers
  8. 7 Power, Reset, Clock Management
    1. 7.1 Power Management
      1. 7.1.1 Power Supply System
        1. 7.1.1.1 VDD_MAIN
        2. 7.1.1.2 VIO
        3. 7.1.1.3 VDDSF
        4. 7.1.1.4 VPA
      2. 7.1.2 Power States
      3. 7.1.3 Power Domains
      4. 7.1.4 Brownout (BOR)
      5. 7.1.5 Boot Sequence
    2. 7.2 Reset
      1. 7.2.1 Reset Cause
      2. 7.2.2 Watchdog Timer (WDT)
    3. 7.3 Clocks
      1. 7.3.1 Fast Clock
      2. 7.3.2 Slow Clock
        1. 7.3.2.1 Slow Clock Overview
        2. 7.3.2.2 Slow Clock Tree
        3. 7.3.2.3 Slow Clock Boot Process
    4. 7.4 PRCM_AON Registers
    5. 7.5 PRCM_SCRATCHPAD Registers
  9. 8 Memory Subsystem (MEMSS)
    1. 8.1  Introduction
    2. 8.2  SRAM
    3. 8.3  D-Cache
    4. 8.4  Flash
    5. 8.5  PSRAM
    6. 8.6  XiP Memory Access
      1. 8.6.1 OTFDE
      2. 8.6.2 xSPI
      3. 8.6.3 Topology
      4. 8.6.4 µDMA
      5. 8.6.5 Arbiter
    7. 8.7  ICACHE Registers
    8. 8.8  DCACHE Registers
    9. 8.9  OSPI Registers
    10. 8.10 HOST_XIP Registers
  10. 9 Hardware Security Module (HSM)
    1. 9.1 Introduction
    2. 9.2 Overview
    3. 9.3 Mailbox and Register Access Firewall
    4. 9.4 DMA Firewall
    5. 9.5 HSM Key Storage
    6. 9.6 HSM Registers
    7. 9.7 HSM_NON_SEC Registers
    8. 9.8 HSM_SEC Registers
  11. 10Device Boot and Bootloader
    1. 10.1 CC35xx Boot Concept
    2. 10.2 Features
    3. 10.3 Vendor Images Format and Processing
      1. 10.3.1 External Flash Arrangement
      2. 10.3.2 Vendor Images Format
    4. 10.4 Boot Flows
      1. 10.4.1 Application Execution Boot Flow
      2. 10.4.2 Activation Flow
      3. 10.4.3 Initial Programming Flow
      4. 10.4.4 Reprogramming Flow
      5. 10.4.5 Wireless Connectivity Testing Tool Flow
    5. 10.5 Chain of Trust
  12. 11Direct Memory Access (DMA)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Channels Assignment
      2. 11.3.2 Transfer Types
      3. 11.3.3 Addressing Modes
      4. 11.3.4 Transfer Modes
      5. 11.3.5 DMA Aligner Support
      6. 11.3.6 Initiating DMA Transfers
      7. 11.3.7 Stopping DMA Transfers
      8. 11.3.8 Channel Priorities
      9. 11.3.9 DMA Interrupts
    4. 11.4 HOST_DMA Registers
  13. 12One Time Programming (OTP)
  14. 13General Purpose Timers (GPT)
    1. 13.1 Overview
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1  Prescaler
      2. 13.3.2  Counter
      3. 13.3.3  Target
      4. 13.3.4  Channel Input Logic
      5. 13.3.5  Channel Output Logic
      6. 13.3.6  Channel Actions
        1. 13.3.6.1 Period and Pulse Width Measurement
        2. 13.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 13.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 13.3.7  Channel Capture Configuration
      8. 13.3.8  Channel Filters
        1. 13.3.8.1 Setting up the Channel Filters
      9. 13.3.9  Synchronize Multiple GPTimers
      10. 13.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 13.4 Timer Modes
      1. 13.4.1 Quadrature Decoder
      2. 13.4.2 DMA
      3. 13.4.3 IR Generation
      4. 13.4.4 Fault and Park
      5. 13.4.5 Dead-Band
      6. 13.4.6 Dead-Band, Fault and Park
      7. 13.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 13.5 GPTIMER Registers
  15. 14System Timer (SysTimer)
    1. 14.1 Overview
    2. 14.2 Block Diagram
    3. 14.3 Functional Description
      1. 14.3.1 Common Channel Features
        1. 14.3.1.1 Compare Mode
        2. 14.3.1.2 Capture Mode
        3. 14.3.1.3 Additional Channel Arming Methods
      2. 14.3.2 Interrupts and Events
    4. 14.4 SYSRESOURCES Registers
    5. 14.5 SYSTIM Registers
  16. 15Real-Time Clock (RTC)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Interrupts and Events
      1. 15.3.1 Input Event
      2. 15.3.2 Output Event
      3. 15.3.3 Arming and Disarming Channels
    4. 15.4 CAPTURE and COMPARE Configurations
      1. 15.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 15.4.2 CHANNEL 1 - CAPTURE CHANNEL
    5. 15.5 RTC Registers
  17. 16General Purpose Input/Output (GPIOs)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 I/O Mapping and Configuration
      1. 16.3.1 Basic I/O Mapping
      2. 16.3.2 Pin Mapping
    4. 16.4 Edge Detection
    5. 16.5 GPIO
    6. 16.6 I/O Pins
    7. 16.7 Unused Pins
    8. 16.8 IOMUX Registers
  18. 17Universal Asynchronous Receivers/Transmitters (UART)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 UART Functional Description
      1. 17.3.1 Transmit and Receive Logic
      2. 17.3.2 Baud Rate Generation
      3. 17.3.3 FIFO Operation
        1. 17.3.3.1 FIFO Remapping
      4. 17.3.4 Data Transmission
      5. 17.3.5 Flow Control
      6. 17.3.6 IrDA Encoding and Decoding
      7. 17.3.7 Interrupts
      8. 17.3.8 Loopback Operation
    4. 17.4 UART-LIN Specification
      1. 17.4.1 Break transmission in UART mode
      2. 17.4.2 Break reception in UART mode
      3. 17.4.3 Break/Synch transmission in LIN mode
      4. 17.4.4 Break/Synch reception in LIN mode
      5. 17.4.5 Dormant mode operation
      6. 17.4.6 Event signal generation
      7. 17.4.7 Event signal detection when device is in active/idle modes
      8. 17.4.8 Event signal detection when device is in sleep mode
    5. 17.5 Interface to Host DMA
    6. 17.6 Initialization and Configuration
    7. 17.7 UART Registers
  19. 18Serial Peripheral Interface (SPI)
    1. 18.1 Overview
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Signal Description
    3. 18.3 Functional Description
      1. 18.3.1  Clock Control
      2. 18.3.2  FIFO Operation
        1. 18.3.2.1 Transmit FIFO
        2. 18.3.2.2 Repeated Transmit Operation
        3. 18.3.2.3 Receive FIFO
        4. 18.3.2.4 FIFO Flush
      3. 18.3.3  Interrupts
      4. 18.3.4  Data Format
      5. 18.3.5  Delayed Data Sampling
      6. 18.3.6  Chip Select Control
      7. 18.3.7  Command Data Control
      8. 18.3.8  Protocol Descriptions
        1. 18.3.8.1 Motorola SPI Frame Format
        2. 18.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 18.3.8.3 MICROWIRE Frame Format
      9. 18.3.9  CRC Configuration
      10. 18.3.10 Auto CRC Functionality
      11. 18.3.11 SPI Status
      12. 18.3.12 Debug Halt
    4. 18.4 Host DMA Operation
    5. 18.5 Initialization and Configuration
    6. 18.6 SPI Registers
  20. 19Inter-Integrated Circuit (I2C) Interface
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Clock Control
        1. 19.3.1.1 Internal Clock
        2. 19.3.1.2 External Clock
      2. 19.3.2 General Architecture
        1. 19.3.2.1  Start and Stop Conditions
        2. 19.3.2.2  Data Format with 7-Bit Address
        3. 19.3.2.3  Data Format with 10-Bit Addressing
          1. 19.3.2.3.1 Additional 10-Bit Scenarios
        4. 19.3.2.4  Acknowledge
        5. 19.3.2.5  Repeated Start
        6. 19.3.2.6  Clock Stretching
        7. 19.3.2.7  Arbitration
        8. 19.3.2.8  Multi-Controller mode
        9. 19.3.2.9  Glitch Suppression
        10. 19.3.2.10 FIFO Operation
        11. 19.3.2.11 Burst Mode Operation
        12. 19.3.2.12 DMA Operation
        13. 19.3.2.13 Flush Stale Tx Data in Target Mode
          1. 19.3.2.13.1 Recommended Sequence
        14. 19.3.2.14 SMBUS 3.0 Support
          1. 19.3.2.14.1 Quick Command
          2. 19.3.2.14.2 Acknowledge Control
          3. 19.3.2.14.3 Alert Response protocol
          4. 19.3.2.14.4 Address Resolution Protocol
          5. 19.3.2.14.5 Enhanced Acknowledge Control
    4. 19.4 Initialization and Configuration
    5. 19.5 Interrupts
    6. 19.6 I2C Registers
  21. 20Secure Digital Multimedia Card (SDMMC)
    1. 20.1 Introduction
      1. 20.1.1 SDMMC Features
      2. 20.1.2 Integration
    2. 20.2 Functional Description
      1. 20.2.1  SDMMC Functional Modes
        1. 20.2.1.1 SDMMC Connected to an SD Card
        2. 20.2.1.2 Protocol and Data Format
          1. 20.2.1.2.1 Protocol
          2. 20.2.1.2.2 Data Format
      2. 20.2.2  SD Card Feedback
      3. 20.2.3  Resets
        1. 20.2.3.1 Hardware Reset
        2. 20.2.3.2 Software Reset
      4. 20.2.4  Interrupt Requests
        1. 20.2.4.1 Interrupt-Driven Operation
        2. 20.2.4.2 Polling
      5. 20.2.5  DMA Modes
        1. 20.2.5.1 DMA Peripheral Mode Operations
          1. 20.2.5.1.1 DMA Receive Mode
          2. 20.2.5.1.2 DMA Transmit Mode
      6. 20.2.6  Buffer Management
        1. 20.2.6.1 Data Buffer
          1. 20.2.6.1.1 Memory Size and Block Length
          2. 20.2.6.1.2 Data Buffer Status
      7. 20.2.7  Transfer Process
        1. 20.2.7.1 Different Types of Commands
        2. 20.2.7.2 Different Types of Responses
      8. 20.2.8  Transfer or Command Status and Error Reporting
        1. 20.2.8.1 Busy Timeout for R1b, R5b Response Type
        2. 20.2.8.2 Busy Timeout After Write CRC Status
        3. 20.2.8.3 Write CRC Status Timeout
        4. 20.2.8.4 Read Data Timeout
      9. 20.2.9  Auto Command 12 Timings
        1. 20.2.9.1 Auto Command 12 Timings During Write Transfer
        2. 20.2.9.2 Auto Command 12 Timings During Read Transfer
      10. 20.2.10 Transfer Stop
      11. 20.2.11 Output Signals Generation
        1. 20.2.11.1 Generation on Falling Edge of SDMMC Clock
        2. 20.2.11.2 Generation on Rising Edge of SDMMC Clock
      12. 20.2.12 Test Registers
      13. 20.2.13 SDMMC Hardware Status Features
    3. 20.3 Low-Level Programming Models
      1. 20.3.1 SDMMC Initialization Flow
        1. 20.3.1.1 Enable OCP and CLKADPI Clocks
        2. 20.3.1.2 SD Soft Reset Flow
        3. 20.3.1.3 Set SD Default Capabilities
        4. 20.3.1.4 SDMMC Host and Bus Configuration
      2. 20.3.2 Operational Modes Configuration
        1. 20.3.2.1 Basic Operations for SDMMC
        2. 20.3.2.2 Card Detection, Identification, and Selection
    4. 20.4 SDMMC Registers
  22. 21Secure Digital Input/Output (SDIO)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 SDIO Interface Description
      2. 21.3.2 Protocol and Data Format
      3. 21.3.3 I/O Read/Write Command
        1. 21.3.3.1 IO_WR_DIRECT Command (CMD52)
        2. 21.3.3.2 IO_WR_EXTENDED Command (CMD53)
      4. 21.3.4 Reset
      5. 21.3.5 FIFO Operation
        1. 21.3.5.1 Rx FIFO (For Host Write)
        2. 21.3.5.2 Tx FIFO (For Host Read)
      6. 21.3.6 Interrupt Request
        1. 21.3.6.1 External Host IRQ
        2. 21.3.6.2 M33 IRQ
      7. 21.3.7 Transaction Details
        1. 21.3.7.1 Host write to SDIO IP (Rx FIFO)
          1. 21.3.7.1.1 Host write to SDIO IP (Rx FIFO) – Long SW latency case
          2. 21.3.7.1.2 Host write to SDIO IP (Rx FIFO) – CRC Error Case
        2. 21.3.7.2 Host reads from SDIO (TX buffer)
    4. 21.4 SDIO_CORE Registers
    5. 21.5 SDIO_CARD_FN1 Registers
  23. 22Inter-Integrated Circuit Sound (I2S)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  Signal Descriptions
    4. 22.4  Functional Description
      1. 22.4.1 Pin Configuration
      2. 22.4.2 Serial Format Configuration
        1. 22.4.2.1 Register Configuration
      3. 22.4.3 Left-Justified (LJF)
        1. 22.4.3.1 Register Configuration
      4. 22.4.4 Right-Justified (RJF)
        1. 22.4.4.1 Register Configuration
      5. 22.4.5 DSP
        1. 22.4.5.1 Register Configuration
      6. 22.4.6 Clock Configuration
    5. 22.5  Memory Interface
      1. 22.5.1 Sample Word Length
      2. 22.5.2 Padding Mechanism
      3. 22.5.3 Channel Mapping
      4. 22.5.4 Sample Storage in Memory
      5. 22.5.5 DMA Operation
        1. 22.5.5.1 Start-Up
        2. 22.5.5.2 Operation
        3. 22.5.5.3 Shutdown
    6. 22.6  Samplestamp Generator
      1. 22.6.1 Samplestamp Counters
      2. 22.6.2 Start-Up Triggers
      3. 22.6.3 Samplestamp Capture
      4. 22.6.4 Achieving constant audio latency
    7. 22.7  Error Detection
    8. 22.8  Usage
      1. 22.8.1 Start-Up Sequence
      2. 22.8.2 Shutdown Sequence
    9. 22.9  I2S Configuration Guideline
    10. 22.10 I2S Registers
  24. 23Pulse Density Modulation (PDM)
    1. 23.1  Introduction
    2. 23.2  Block Diagram
    3. 23.3  Input Selection
      1. 23.3.1 PDM Data Mode
      2. 23.3.2 Manchester Input Mode
    4. 23.4  CIC Filter
      1. 23.4.1 Filter Design
      2. 23.4.2 Digital Filter Output
      3. 23.4.3 Offset Binary Mode
      4. 23.4.4 Twos-Complement Mode
    5. 23.5  FIFO Organization in Different Modes
      1. 23.5.1 Single Mono Microphone Configuration
        1. 23.5.1.1 24-bit Sample Size
          1. 23.5.1.1.1 32-bit Data Read
        2. 23.5.1.2 16-bit Sample Size
          1. 23.5.1.2.1 32-bit Data Read
          2. 23.5.1.2.2 16-bit Data Read
        3. 23.5.1.3 8-bit Sample Size
          1. 23.5.1.3.1 32-bit Data Read
          2. 23.5.1.3.2 16-bit Data Read
          3. 23.5.1.3.3 8-bit Data Read
      2. 23.5.2 Stereo or Dual Mono Microphone Configuration
        1. 23.5.2.1 24-bit Sample Size
          1. 23.5.2.1.1 32-bit Data Read
        2. 23.5.2.2 16-bit Sample Size
          1. 23.5.2.2.1 32-bit Data Read
          2. 23.5.2.2.2 16-bit Data Read
        3. 23.5.2.3 8-bit Sample Size
          1. 23.5.2.3.1 32-bit Data Read
          2. 23.5.2.3.2 16-bit Data Read
          3. 23.5.2.3.3 8-bit Data Read
      3. 23.5.3 FIFO Threshold Setting
      4. 23.5.4 Reset FIFO
    6. 23.6  Automatic Gain Control (AGC)
      1. 23.6.1 Operation in 2's Complement Format
      2. 23.6.2 Operation in Offset Binary Format
    7. 23.7  Interrupts
    8. 23.8  Clock Select and Control
    9. 23.9  DMA Operation
    10. 23.10 Samplestamp Generator
      1. 23.10.1 Samplestamp Counters
      2. 23.10.2 Start-Up Triggers
      3. 23.10.3 Samplestamp Capture
      4. 23.10.4 Achieving Constant Audio Latency
    11. 23.11 Debug‑Mode Flag Behavior
    12. 23.12 Software Guidelines
    13. 23.13 PDM Registers
  25. 24Analog to Digital Converter (ADC)
    1. 24.1 Overview
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1  ADC Core
      2. 24.3.2  Voltage Reference Options
      3. 24.3.3  Internal Channels
      4. 24.3.4  Resolution Modes
      5. 24.3.5  ADC Clocking
      6. 24.3.6  Power Down Behavior
      7. 24.3.7  Sampling Trigger Sources and Sampling Modes
        1. 24.3.7.1 AUTO Sampling Mode
        2. 24.3.7.2 MANUAL Sampling Mode
      8. 24.3.8  Sampling Period
      9. 24.3.9  Conversion Modes
      10. 24.3.10 ADC Data Format
      11. 24.3.11 Status Register
      12. 24.3.12 ADC Events
        1. 24.3.12.1 Generic Event Publishers (INT_EVENT0 & INT_EVENT1)
        2. 24.3.12.2 DMA Trigger Event Publisher (INT_EVENT2)
        3. 24.3.12.3 Generic Event Subscriber
      13. 24.3.13 Advanced Features
        1. 24.3.13.1 Window Comparator
        2. 24.3.13.2 DMA & FIFO Operation
          1. 24.3.13.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
          2. 24.3.13.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
          3. 24.3.13.2.3 DMA/CPU Operation Summary Matrix
        3. 24.3.13.3 Ad-hoc Single Conversion
    4. 24.4 ADC Registers
  26. 25Controller Area Network (CAN)
    1. 25.1 Introduction
    2. 25.2 Functions
    3. 25.3 DCAN Subsystem
    4. 25.4 DCAN Functional Description
      1. 25.4.1 Operating Modes
        1. 25.4.1.1 Software Initialization
        2. 25.4.1.2 Normal Operation
        3. 25.4.1.3 Restricted Operation Mode
        4. 25.4.1.4 Bus Monitoring Mode
        5. 25.4.1.5 Disabled Automatic Retransmission
          1. 25.4.1.5.1 Frame Transmission in DAR Mode
        6. 25.4.1.6 Power Down (Sleep Mode)
          1. 25.4.1.6.1 DCAN clock stop and wake operations
          2. 25.4.1.6.2 DCAN debug suspend operation
        7. 25.4.1.7 Test Modes
          1. 25.4.1.7.1 External Loop Back Mode
          2. 25.4.1.7.2 Internal Loop Back Mode
      2. 25.4.2 Timestamp Generation
        1. 25.4.2.1 Block Diagram
      3. 25.4.3 Timeout Counter
      4. 25.4.4 Rx Handling
        1. 25.4.4.1 Acceptance Filtering
          1. 25.4.4.1.1 Range Filter
          2. 25.4.4.1.2 Filter for specific IDs
          3. 25.4.4.1.3 Classic Bit Mask Filter
          4. 25.4.4.1.4 Standard Message ID Filtering
          5. 25.4.4.1.5 Extended Message ID Filtering
        2. 25.4.4.2 Rx FIFOs
          1. 25.4.4.2.1 Rx FIFO Blocking Mode
          2. 25.4.4.2.2 Rx FIFO Overwrite Mode
        3. 25.4.4.3 Dedicated Rx Buffers
          1. 25.4.4.3.1 Rx Buffer Handling
        4. 25.4.4.4 Debug on CAN Support
          1. 25.4.4.4.1 Filtering for Debug Messages
          2. 25.4.4.4.2 Debug Message Handling
      5. 25.4.5 Tx Handling
        1. 25.4.5.1 Transmit Pause
        2. 25.4.5.2 Dedicated Tx Buffers
        3. 25.4.5.3 Tx FIFO
        4. 25.4.5.4 Tx Queue
        5. 25.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 25.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 25.4.5.7 Transmit Cancellation
        8. 25.4.5.8 Tx Event Handling
      6. 25.4.6 FIFO Acknowledge Handling
      7. 25.4.7 DCAN Message RAM
        1. 25.4.7.1 Message RAM Configuration
        2. 25.4.7.2 Rx Buffer and FIFO Element
        3. 25.4.7.3 Tx Buffer Element
        4. 25.4.7.4 Tx Event FIFO Element
        5. 25.4.7.5 Standard Message ID Filter Element
        6. 25.4.7.6 Extended Message ID Filter Element
      8. 25.4.8 Interrupt Requests
    5. 25.5 DCAN Wrapper
    6. 25.6 DCAN Clock Enable
    7. 25.7 DCAN Registers
  27. 26Revision History

14.5 SYSTIM Registers

Table 14-6 lists the memory-mapped registers for the SYSTIM registers. All register offset addresses not listed in Table 14-6 should be considered as reserved locations and the register contents should not be modified.

Table 14-6 SYSTIM Registers
OffsetAcronymRegister NameSection
0hDESCModule IdentificationSection 14.5.1
44hIBMInterrupt MaskSection 14.5.2
48hRISInterrupt Status FlagsSection 14.5.3
4ChMISMasked interrupt statusSection 14.5.4
50hISETInterrupt SetSection 14.5.5
54hICLRInterrupt ClearSection 14.5.6
58hIMSETInterrupt Mask SetSection 14.5.7
5ChIMCLRInterrupt Mask ClearSection 14.5.8
60hEMUEmulation ControlSection 14.5.9
100hTIME250NCounter Low ValueSection 14.5.10
104hTIME1USystem Timer CountSection 14.5.11
108hOUTOutput ValuesSection 14.5.12
10ChCH0CFGChannel ConfigurationSection 14.5.13
110hCH1CFGChannel ConfigurationSection 14.5.14
120hCH0CCCompare ValueSection 14.5.15
124hCH1CCChannel1 reg ValueSection 14.5.16
134hTIMEBITSystem Timer BitSection 14.5.17
138hKPProportional GainSection 14.5.18
13ChKIIntegral Gain CoefficientSection 14.5.19
140hSTATimer StatusSection 14.5.20
144hARMSETArm Status SetSection 14.5.21
148hARMCLRArm Clear StatusSection 14.5.22
14ChCH0CCSRChannel Value AliasSection 14.5.23
150hCH1CCSRChannel 1 ValueSection 14.5.24
1000hCLKCFGClock EnableSection 14.5.25

Complex bit access types are encoded to fit into small table cells. Table 14-7 shows the codes that are used for access types in this section.

Table 14-7 SYSTIM Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RmodifyR
modify		Read
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

14.5.1 DESC Register (Offset = 0h) [Reset = 94431010h]

DESC is shown in Table 14-8.

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This register identifies the peripheral and its exact version.

Table 14-8 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDR9443hModule identifier MODID[15:0]. Used to uniquely identify this IP. See comment about derivation below
  • 0h = Smallest value
  • FFFFh = Highest possible value
15-12STDIPOFFR1h64 B standard IP MMR block (beginning with aggregated IRQ registers) 0: STDIP MMRs do not exist 1:15: These MMRs begin at offset 64*STDIPOFF from IP base address
  • 0h = Smallest value
  • Fh = Highest possible value
11-8INSTIDXR0hIf multiple instances of IP exists in SOC, this field can identify the instance number 0-15
  • 0h = Smallest value
  • Fh = Highest possible value
7-4MAJREVR1hMajor revision of IP 0-15
  • 0h = Smallest value
  • Fh = Highest possible value
3-0MINREVR0hMinor revision of IP 0-15.
  • 0h = Smallest value
  • Fh = Highest possible value

14.5.2 IBM Register (Offset = 44h) [Reset = 00000000h]

IBM is shown in Table 14-9.

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INTERRUPT BIT MASK Interrupt Mask. If a bit is cleared, then corresponding interrupt is masked.

Table 14-9 IBM Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6OVFLR/W0hMask Timer Overflow Event in MIS register.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
5-2RESERVEDR0hReserved
1EVT1R/W0hMask EVENT1 in MIS register.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
0EVT0R/W0hMask EVENT0 in MIS register.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask

14.5.3 RIS Register (Offset = 48h) [Reset = 00000000h]

RIS is shown in Table 14-10.

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Raw interrupt status reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Table 14-10 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6OVFLR0hRaw interrupt status for Timer Overflow EVENT. This bit is set to 1 when an event is received on Timer Ovreflow EVENT channel.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
5-2RESERVEDR0hReserved
1EVT1R0hRaw interrupt status for EVENT1. This bit is set to 1 when an event is received on EVENT1 channel.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
0EVT0R0hRaw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured

14.5.4 MIS Register (Offset = 4Ch) [Reset = 00000000h]

MIS is shown in Table 14-11.

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Masked interrupt status. This is an AND of the IMASK and RIS registers.

Table 14-11 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6OVFLR0hMask Interrupt Status Timer Overflow Event in MIS register.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
5-2RESERVEDR0hReserved
1EVT1R0hMask interrupt status for EVENT1
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
0EVT0R0hMask interrupt status for EVENT0
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured

14.5.5 ISET Register (Offset = 50h) [Reset = 00000000h]

ISET is shown in Table 14-12.

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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Table 14-12 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6OVFLW0hSets Timer Overflow EVENT in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
5-2RESERVEDR0hReserved
1EVT1W0hSets channel1 EVENT in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
0EVT0W0hSets channel0 EVENT in RIS
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt

14.5.6 ICLR Register (Offset = 54h) [Reset = 00000000h]

ICLR is shown in Table 14-13.

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Interrupt clear. Write a 1 to clear corresponding Interrupt.

Table 14-13 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6OVFLW0hOverflow
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
5-2RESERVEDR0hReserved
1EVT1W0hClears EVENT1 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
0EVT0W0hClears EVENT0 in RIS
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt

14.5.7 IMSET Register (Offset = 58h) [Reset = 00000000h]

IMSET is shown in Table 14-14.

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Interrupt mask set. Writing a 1 to a bit in IMSET will set the related IMASK bit.

Table 14-14 IMSET Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6OVFLW0hSets Timer Overflow Event.
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
5-2RESERVEDR0hReserved
1EVT1W0hSets channel1 Event
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
0EVT0W0hSets channel0 Event
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask

14.5.8 IMCLR Register (Offset = 5Ch) [Reset = 00000000h]

IMCLR is shown in Table 14-15.

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Interrupt mask clear. Writing a 1 to a bit in IMCLR will clear the related IMASK bit.

Table 14-15 IMCLR Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6OVFLW0hClears Timer Overflow Event.
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
5-2RESERVEDR0hReserved
1EVT1W0hClears channel1 Event.
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
0EVT0W0hClears channel0 Event.
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask

14.5.9 EMU Register (Offset = 60h) [Reset = 00000000h]

EMU is shown in Table 14-16.

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This register can be used by the software developer to control the behavior of the peripheral relative to the CPU Halted input.

Table 14-16 EMU Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0HALTR/W0hThis bit controls peripheral behavior at CPU halt condition.
  • 0h = Peripheral ignores the state of the CPU Halted input
  • 1h = Peripheral freezes functionality immediately or at appropriate time when the CPU Halted input is asserted and resumes when it is deasserted

14.5.10 TIME250N Register (Offset = 100h) [Reset = 00000000h]

TIME250N is shown in Table 14-17.

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Systimer Counter Value[31:0]. Time with 250ns resolution from systimer

Table 14-17 TIME250N Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR0hCounter Value. This is not writable while the systimer counter is enabled
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

14.5.11 TIME1U Register (Offset = 104h) [Reset = 00000000h]

TIME1U is shown in Table 14-18.

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Systimer Counter Value[33:2]. Time with 1us resolution from systimer

Table 14-18 TIME1U Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR0hCounter Value. This is not writable while the systimer counter is enabled
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

14.5.12 OUT Register (Offset = 108h) [Reset = 00000000h]

OUT is shown in Table 14-19.

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SYSTIMER'S Channel Output Event Values

Table 14-19 OUT Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1OUT1R0hOutput Value of channel 1.
  • 0h = Event did not occur.
  • 1h = Event occured
0OUT0R0hOutput Value of channel 0.
  • 0h = Event did not occur.
  • 1h = Event occured

14.5.13 CH0CFG Register (Offset = 10Ch) [Reset = 00000000h]

CH0CFG is shown in Table 14-20.

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SYSTIMER channel 0 configuration

Table 14-20 CH0CFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4RESR/W0hThis bit decides the RESOLUTION of the channel that will be used.
  • 0h = Channel Works in Timer's 1us Resolution.
  • 1h = Channel Works in Timer's 250ns resolution
3REARMR/W0hWhen Rearm is enabled the channel remains in continuous capture mode. Otherwise it'll be in One shot capture mode. Rearm is only valid for capture mode.
  • 0h = Re Arm is disabled
  • 1h = Re arm is enabled
2-1INPR/W0hDecides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function.
  • 0h = Capture on rising edge
  • 1h = Capture on Falling Edge
  • 2h = Capture on both Edge
0MODER/W0hDecides the channel mode.
  • 0h = Channel is disabled
  • 1h = Channel is in capture mode

14.5.14 CH1CFG Register (Offset = 110h) [Reset = 00000000h]

CH1CFG is shown in Table 14-21.

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SYSTIMER channel 1 configuration

Table 14-21 CH1CFG Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3REARMR/W0hWhen Rearm is enabled the channel remains in continous capture mode. Otherwise it'll be in One shot capture mode. Rearm is only valid for capture mode.
  • 0h = Re Arm is disabled
  • 1h = Re arm is enabled
2-1INPR/W0hDecides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function
  • 0h = Capture on rising edge
  • 1h = Capture on Falling Edge
  • 2h = Capture on both Edge
0MODER/W0hDecides the channel mode.
  • 0h = Channel is disabled
  • 1h = Channel is in capture mode

14.5.15 CH0CC Register (Offset = 120h) [Reset = 00000000h]

CH0CC is shown in Table 14-22.

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System Timer Channel 0 Capture/Compare Register. This Register when written with any compare value will arm the channel to work in compare mode.

Table 14-22 CH0CC Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hCapture/compare value
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

14.5.16 CH1CC Register (Offset = 124h) [Reset = 00000000h]

CH1CC is shown in Table 14-23.

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System Timer Channel 1 Capture/Compare Register. This Register when written with any compare value will arm the channel to work in compare mode.

Table 14-23 CH1CC Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hCapture/compare value
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

14.5.17 TIMEBIT Register (Offset = 134h) [Reset = 00000000h]

TIMEBIT is shown in Table 14-24.

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This Register will be used to specify which TIME bit is required by LGPT to be forwarded from SYSTIMER.

Table 14-24 TIMEBIT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hThe corresponding bit will have value '1' rest should be '0'. If more than one bit is asserted, output is "or" of all the bits.
  • 0h = No bit is forwarded to the event fabric.
  • 1h = Bit2 is forwarded to the event fabric.
  • 2h = Bit3 is forwarded to the event fabric.
  • 4h = Bit4 is forwarded to the event fabric.
  • 8h = Bit5 is forwarded to the event fabric.
  • 10h = Bit6 is forwarded to the event fabric.
  • 20h = Bit7 is forwarded to the event fabric.
  • 40h = Bit8 is forwarded to the event fabric.
  • 80h = Bit9 is forwarded to the event fabric.
  • 100h = Bit10 is forwarded to the event fabric.
  • 200h = Bit11 is forwarded to the event fabric.
  • 400h = Bit12 is forwarded to the event fabric.
  • 800h = Bit13 is forwarded to the event fabric.
  • 1000h = Bit14 is forwarded to the event fabric.
  • 2000h = Bit15 is forwarded to the event fabric.
  • 4000h = Bit16 is forwarded to the event fabric.
  • 8000h = Bit17 is forwarded to the event fabric.

14.5.18 KP Register (Offset = 138h) [Reset = 00000004h]

KP is shown in Table 14-25.

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PI filter's Proportional Gain Value

Table 14-25 KP Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0VALR/W4hProportional Error is left shifted by this value.
  • 0h = Smallest value
  • Fh = Highest possible value

14.5.19 KI Register (Offset = 13Ch) [Reset = 00000001h]

KI is shown in Table 14-26.

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PI filter's Accumulator's Gain Value

Table 14-26 KI Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0VALR/W1hAccumulated Error is left shifted by this value.
  • 0h = Smallest value
  • Fh = Highest possible value

14.5.20 STA Register (Offset = 140h) [Reset = 00000010h]

STA is shown in Table 14-27.

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STATUS This is the system timer status register.

Table 14-27 STA Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4SYNCUPR1hThis bit indicates the status of resyncup of systimer with RTC. The bitfield has a reset value of '1' , as out of reset the systimer syncs up with RTC, after the first_synced_lftick occurs the SYNCUP bit goes to zero.
  • 0h = SYNC UP with RTC is not happening
  • 1h = Any write to STATUS register, triggers the SYNCUP with RTC and this bit is set.
3-1RESERVEDR0hReserved
0VALR0h This bit indicates if the system time is initialized and running.
  • 0h = system timer is not running.
  • 1h = system timer is running

14.5.21 ARMSET Register (Offset = 144h) [Reset = 00000000h]

ARMSET is shown in Table 14-28.

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ARMSET on read gives out the status of the 2 channels 1. Channel state UNARMED returns 0 2. Channel state CAPTURE or COMPARE returns 1 A write to ARMSET has for each channel the following effect: 1. If ARMSTA[x]==0 -> no effect 2. If ARMSTA[x]==1 and channel x is in CAPTURE state then no effect on the channel 3. Else Set channel in COMPARE mode using existing CHxVAL value

Table 14-28 ARMSET Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1CH1R/W0hArming Channel 1 for either compare or capture operation.
  • 0h = No effect on the channel
  • 1h = if channel 1 is in CAPTURE state then no effect on the channel Else ; Set channel in COMPARE mode using existing CH1VAL value
0CH0R/W0hArming Channel 0 for either compare or capture operation.
  • 0h = No effect on the channel
  • 1h = if channel 0 is in CAPTURE state then no effect on the channel 3. Else ; Set channel in COMPARE mode using existing CH0VAL value

14.5.22 ARMCLR Register (Offset = 148h) [Reset = 00000000h]

ARMCLR is shown in Table 14-29.

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ARMCLR on read gives out the status of the 2 channels 1. Channel state UNARMED returns 0 2. Channel state CAPTURE or COMPARE returns 1 A write to ARMCLR has for each channel the following effect: 1. If ARMCLR[x]==0 no effect 2. Else Set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle

Table 14-29 ARMCLR Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1CH1R/W0hDisarming Channel 1
  • 0h = No effect on the channel
  • 1h = Set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle
0CH0R/W0hDisarming Channel 0
  • 0h = No effect on the channel
  • 1h = Set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle

14.5.23 CH0CCSR Register (Offset = 14Ch) [Reset = 00000000h]

CH0CCSR is shown in Table 14-30.

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Save/restore alias registers Channel 0. i. A read to CH0SR behaves exactly as a read to CH0VAL. A write to CH0SR sets CH0VAL value of register without affecting channel state or configuration

Table 14-30 CH0CCSR Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hCapture/compare value
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

14.5.24 CH1CCSR Register (Offset = 150h) [Reset = 00000000h]

CH1CCSR is shown in Table 14-31.

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Save/restore alias registers Channel 1. i. A read to CH1SR behaves exactly as a read to CH1VAL. A write to CH1SR sets CH1VAL value of register without affecting channel state or configuration.

Table 14-31 CH1CCSR Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hCapture/compare value
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

14.5.25 CLKCFG Register (Offset = 1000h) [Reset = 00000000h]

CLKCFG is shown in Table 14-32.

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CLOCK CONFIG

Table 14-32 CLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ENRmodify/W0hENABLE '1' - enable systimer clk '0' - disable systimer clk
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value