SWRU626 December   2025 CC3501E , CC3551E

 

  1.   1
  2. 1 Read This First
    1. 1.1 About This Manual
    2. 1.2 Register, Field, and Bit Calls
    3.     Trademarks
  3. 2 Architecture Overview
    1. 2.1  Target Applications
    2. 2.2  Introduction
    3. 2.3  Internal System Diagram
    4. 2.4  Arm Cortex M33
      1. 2.4.1 Processor Core
      2. 2.4.2 SysTick Timer
      3. 2.4.3 Nested Vectored Interrupt Controller
      4. 2.4.4 System Control Block (SCB)
      5. 2.4.5 TI AI instruction extensions
    5. 2.5  Power Management
      1. 2.5.1 VDD_MAIN
      2. 2.5.2 VDD_IO
      3. 2.5.3 VDDSF
      4. 2.5.4 VDD_PA
    6. 2.6  Debug Subsystem (DEBUGSS)
    7. 2.7  Memory Subsystem (MEMSS)
      1. 2.7.1 External Memory Interface
    8. 2.8  Hardware Security Module
    9. 2.9  General Purpose Timers (GPT)
    10. 2.10 Real Time Clock (RTC)
    11. 2.11 Direct Memory Access
    12. 2.12 GPIOs
    13. 2.13 Communication Peripherals
      1. 2.13.1 UART
      2. 2.13.2 I2C
      3. 2.13.3 SPI
      4. 2.13.4 I2S
      5. 2.13.5 SDMMC
      6. 2.13.6 SDIO
      7. 2.13.7 CAN
      8. 2.13.8 ADC
  4. 3  Arm Cortex-M33 Processor
    1. 3.1 Arm Cortex-M33 Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 M33 instantiation parameters
    4. 3.4 Arm Cortex-M33 System Peripheral Details
      1. 3.4.1 Floating Point Unit (FPU)
      2. 3.4.2 Memory Protection Unit (MPU)
      3. 3.4.3 Digital Signal Processing (DSP)
      4. 3.4.4 Security Attribution Unit (SAU)
      5. 3.4.5 System Timer
      6. 3.4.6 Nested Vectored Interrupt Controller
      7. 3.4.7 System Control Block
      8. 3.4.8 System Control Space
    5. 3.5 CPU Sub-System Peripheral Details
      1. 3.5.1 Trace Port Interface Unit (TPIU)
      2. 3.5.2 DAP Bridge and Debug Authentication
      3. 3.5.3 Implementation Defined Attribution Unit (IDAU)
    6. 3.6 Programming Model
      1. 3.6.1 Modes of operation and execution
        1. 3.6.1.1 Security states
        2. 3.6.1.2 Operating modes
        3. 3.6.1.3 Operating states
        4. 3.6.1.4 Privileged access and unprivileged user access
      2. 3.6.2 Instruction set summary
      3. 3.6.3 Memory model
        1. 3.6.3.1 Private Peripheral Bus
        2. 3.6.3.2 Unaligned accesses
      4. 3.6.4 Processor core registers summary
      5. 3.6.5 Exceptions
        1. 3.6.5.1 Exception handling and prioritization
    7. 3.7 TrustZone-M
      1. 3.7.1 Overview
      2. 3.7.2 M33 Configuration
      3. 3.7.3 Description of elements
        1. 3.7.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 3.7.3.1.1 Expected use
    8. 3.8 CC35xx Host MCU Registers
      1. 3.8.1 HOSTMCU_AON Registers
      2. 3.8.2 HOST_MCU Registers
      3. 3.8.3 HOST_MCU_SEC Registers
    9. 3.9 Arm® Cortex®-M33 Registers
      1. 3.9.1  CPU_ROM_TABLE Registers
      2. 3.9.2  TPIU Registers
      3. 3.9.3  DCB Registers
      4. 3.9.4  DIB Registers
      5. 3.9.5  DWT Registers
      6. 3.9.6  FPB Registers
      7. 3.9.7  FPE Registers
      8. 3.9.8  ICB Registers
      9. 3.9.9  ITM Registers
      10. 3.9.10 MPU Registers
      11. 3.9.11 NVIC Registers
      12. 3.9.12 SAU Registers
      13. 3.9.13 SCB Registers
      14. 3.9.14 SYSTIMER Registers
      15. 3.9.15 SYSTICK Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation to HardFault
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Manager
      1. 5.4.1 Introduction
      2. 5.4.2 Interrupts List
      3. 5.4.3 Wakeup Sources
      4. 5.4.4 Shared Peripherals MUX Selector
        1. 5.4.4.1 ADC HW Event Selector Mux
        2. 5.4.4.2 I2S HW Event Selector Mux
        3. 5.4.4.3 PDM HW Event Selector Mux
      5. 5.4.5 Timers MUX Selector Mux
        1. 5.4.5.1 SysTimer0 HW Event Selector Mux
        2. 5.4.5.2 SysTimer1 HW Event Selector Mux
        3. 5.4.5.3 RTC HW Event Selector Mux
      6. 5.4.6 GPTIMERs MUX Selector Mux
        1. 5.4.6.1 GPTIMER0 HW Event Selector Mux
        2. 5.4.6.2 GPTIMER1 HW Event Selector Mux
    5. 5.5 SOC_IC Registers
    6. 5.6 SOC_AON Registers
    7. 5.7 SOC_AAON Registers
  7. 6 Debug Subsystem (DEBUGSS)
    1. 6.1 Introduction
    2. 6.2 Block Diagram
    3. 6.3 Overview
    4. 6.4 Physical Interface
    5. 6.5 Debug Access Ports
    6. 6.6 Debug Features
      1. 6.6.1 Processor Debug
      2. 6.6.2 Breakpoint Unit (BPU)
      3. 6.6.3 Peripheral Debug
    7. 6.7 Behavior in Low Power Modes
    8. 6.8 Debug Access Control
    9. 6.9 SOC_DEBUGSS Registers
  8. 7 Power, Reset, Clock Management
    1. 7.1 Power Management
      1. 7.1.1 Power Supply System
        1. 7.1.1.1 VDD_MAIN
        2. 7.1.1.2 VIO
        3. 7.1.1.3 VDDSF
        4. 7.1.1.4 VPA
      2. 7.1.2 Power States
      3. 7.1.3 Power Domains
      4. 7.1.4 Brownout (BOR)
      5. 7.1.5 Boot Sequence
    2. 7.2 Reset
      1. 7.2.1 Reset Cause
      2. 7.2.2 Watchdog Timer (WDT)
    3. 7.3 Clocks
      1. 7.3.1 Fast Clock
      2. 7.3.2 Slow Clock
        1. 7.3.2.1 Slow Clock Overview
        2. 7.3.2.2 Slow Clock Tree
        3. 7.3.2.3 Slow Clock Boot Process
    4. 7.4 PRCM_AON Registers
    5. 7.5 PRCM_SCRATCHPAD Registers
  9. 8 Memory Subsystem (MEMSS)
    1. 8.1  Introduction
    2. 8.2  SRAM
    3. 8.3  D-Cache
    4. 8.4  Flash
    5. 8.5  PSRAM
    6. 8.6  XiP Memory Access
      1. 8.6.1 OTFDE
      2. 8.6.2 xSPI
      3. 8.6.3 Topology
      4. 8.6.4 µDMA
      5. 8.6.5 Arbiter
    7. 8.7  ICACHE Registers
    8. 8.8  DCACHE Registers
    9. 8.9  OSPI Registers
    10. 8.10 HOST_XIP Registers
  10. 9 Hardware Security Module (HSM)
    1. 9.1 Introduction
    2. 9.2 Overview
    3. 9.3 Mailbox and Register Access Firewall
    4. 9.4 DMA Firewall
    5. 9.5 HSM Key Storage
    6. 9.6 HSM Registers
    7. 9.7 HSM_NON_SEC Registers
    8. 9.8 HSM_SEC Registers
  11. 10Device Boot and Bootloader
    1. 10.1 CC35xx Boot Concept
    2. 10.2 Features
    3. 10.3 Vendor Images Format and Processing
      1. 10.3.1 External Flash Arrangement
      2. 10.3.2 Vendor Images Format
    4. 10.4 Boot Flows
      1. 10.4.1 Application Execution Boot Flow
      2. 10.4.2 Activation Flow
      3. 10.4.3 Initial Programming Flow
      4. 10.4.4 Reprogramming Flow
      5. 10.4.5 Wireless Connectivity Testing Tool Flow
    5. 10.5 Chain of Trust
  12. 11Direct Memory Access (DMA)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Channels Assignment
      2. 11.3.2 Transfer Types
      3. 11.3.3 Addressing Modes
      4. 11.3.4 Transfer Modes
      5. 11.3.5 DMA Aligner Support
      6. 11.3.6 Initiating DMA Transfers
      7. 11.3.7 Stopping DMA Transfers
      8. 11.3.8 Channel Priorities
      9. 11.3.9 DMA Interrupts
    4. 11.4 HOST_DMA Registers
  13. 12One Time Programming (OTP)
  14. 13General Purpose Timers (GPT)
    1. 13.1 Overview
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1  Prescaler
      2. 13.3.2  Counter
      3. 13.3.3  Target
      4. 13.3.4  Channel Input Logic
      5. 13.3.5  Channel Output Logic
      6. 13.3.6  Channel Actions
        1. 13.3.6.1 Period and Pulse Width Measurement
        2. 13.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 13.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 13.3.7  Channel Capture Configuration
      8. 13.3.8  Channel Filters
        1. 13.3.8.1 Setting up the Channel Filters
      9. 13.3.9  Synchronize Multiple GPTimers
      10. 13.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 13.4 Timer Modes
      1. 13.4.1 Quadrature Decoder
      2. 13.4.2 DMA
      3. 13.4.3 IR Generation
      4. 13.4.4 Fault and Park
      5. 13.4.5 Dead-Band
      6. 13.4.6 Dead-Band, Fault and Park
      7. 13.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 13.5 GPTIMER Registers
  15. 14System Timer (SysTimer)
    1. 14.1 Overview
    2. 14.2 Block Diagram
    3. 14.3 Functional Description
      1. 14.3.1 Common Channel Features
        1. 14.3.1.1 Compare Mode
        2. 14.3.1.2 Capture Mode
        3. 14.3.1.3 Additional Channel Arming Methods
      2. 14.3.2 Interrupts and Events
    4. 14.4 SYSRESOURCES Registers
    5. 14.5 SYSTIM Registers
  16. 15Real-Time Clock (RTC)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Interrupts and Events
      1. 15.3.1 Input Event
      2. 15.3.2 Output Event
      3. 15.3.3 Arming and Disarming Channels
    4. 15.4 CAPTURE and COMPARE Configurations
      1. 15.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 15.4.2 CHANNEL 1 - CAPTURE CHANNEL
    5. 15.5 RTC Registers
  17. 16General Purpose Input/Output (GPIOs)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 I/O Mapping and Configuration
      1. 16.3.1 Basic I/O Mapping
      2. 16.3.2 Pin Mapping
    4. 16.4 Edge Detection
    5. 16.5 GPIO
    6. 16.6 I/O Pins
    7. 16.7 Unused Pins
    8. 16.8 IOMUX Registers
  18. 17Universal Asynchronous Receivers/Transmitters (UART)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 UART Functional Description
      1. 17.3.1 Transmit and Receive Logic
      2. 17.3.2 Baud Rate Generation
      3. 17.3.3 FIFO Operation
        1. 17.3.3.1 FIFO Remapping
      4. 17.3.4 Data Transmission
      5. 17.3.5 Flow Control
      6. 17.3.6 IrDA Encoding and Decoding
      7. 17.3.7 Interrupts
      8. 17.3.8 Loopback Operation
    4. 17.4 UART-LIN Specification
      1. 17.4.1 Break transmission in UART mode
      2. 17.4.2 Break reception in UART mode
      3. 17.4.3 Break/Synch transmission in LIN mode
      4. 17.4.4 Break/Synch reception in LIN mode
      5. 17.4.5 Dormant mode operation
      6. 17.4.6 Event signal generation
      7. 17.4.7 Event signal detection when device is in active/idle modes
      8. 17.4.8 Event signal detection when device is in sleep mode
    5. 17.5 Interface to Host DMA
    6. 17.6 Initialization and Configuration
    7. 17.7 UART Registers
  19. 18Serial Peripheral Interface (SPI)
    1. 18.1 Overview
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Signal Description
    3. 18.3 Functional Description
      1. 18.3.1  Clock Control
      2. 18.3.2  FIFO Operation
        1. 18.3.2.1 Transmit FIFO
        2. 18.3.2.2 Repeated Transmit Operation
        3. 18.3.2.3 Receive FIFO
        4. 18.3.2.4 FIFO Flush
      3. 18.3.3  Interrupts
      4. 18.3.4  Data Format
      5. 18.3.5  Delayed Data Sampling
      6. 18.3.6  Chip Select Control
      7. 18.3.7  Command Data Control
      8. 18.3.8  Protocol Descriptions
        1. 18.3.8.1 Motorola SPI Frame Format
        2. 18.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 18.3.8.3 MICROWIRE Frame Format
      9. 18.3.9  CRC Configuration
      10. 18.3.10 Auto CRC Functionality
      11. 18.3.11 SPI Status
      12. 18.3.12 Debug Halt
    4. 18.4 Host DMA Operation
    5. 18.5 Initialization and Configuration
    6. 18.6 SPI Registers
  20. 19Inter-Integrated Circuit (I2C) Interface
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Clock Control
        1. 19.3.1.1 Internal Clock
        2. 19.3.1.2 External Clock
      2. 19.3.2 General Architecture
        1. 19.3.2.1  Start and Stop Conditions
        2. 19.3.2.2  Data Format with 7-Bit Address
        3. 19.3.2.3  Data Format with 10-Bit Addressing
          1. 19.3.2.3.1 Additional 10-Bit Scenarios
        4. 19.3.2.4  Acknowledge
        5. 19.3.2.5  Repeated Start
        6. 19.3.2.6  Clock Stretching
        7. 19.3.2.7  Arbitration
        8. 19.3.2.8  Multi-Controller mode
        9. 19.3.2.9  Glitch Suppression
        10. 19.3.2.10 FIFO Operation
        11. 19.3.2.11 Burst Mode Operation
        12. 19.3.2.12 DMA Operation
        13. 19.3.2.13 Flush Stale Tx Data in Target Mode
          1. 19.3.2.13.1 Recommended Sequence
        14. 19.3.2.14 SMBUS 3.0 Support
          1. 19.3.2.14.1 Quick Command
          2. 19.3.2.14.2 Acknowledge Control
          3. 19.3.2.14.3 Alert Response protocol
          4. 19.3.2.14.4 Address Resolution Protocol
          5. 19.3.2.14.5 Enhanced Acknowledge Control
    4. 19.4 Initialization and Configuration
    5. 19.5 Interrupts
    6. 19.6 I2C Registers
  21. 20Secure Digital Multimedia Card (SDMMC)
    1. 20.1 Introduction
      1. 20.1.1 SDMMC Features
      2. 20.1.2 Integration
    2. 20.2 Functional Description
      1. 20.2.1  SDMMC Functional Modes
        1. 20.2.1.1 SDMMC Connected to an SD Card
        2. 20.2.1.2 Protocol and Data Format
          1. 20.2.1.2.1 Protocol
          2. 20.2.1.2.2 Data Format
      2. 20.2.2  SD Card Feedback
      3. 20.2.3  Resets
        1. 20.2.3.1 Hardware Reset
        2. 20.2.3.2 Software Reset
      4. 20.2.4  Interrupt Requests
        1. 20.2.4.1 Interrupt-Driven Operation
        2. 20.2.4.2 Polling
      5. 20.2.5  DMA Modes
        1. 20.2.5.1 DMA Peripheral Mode Operations
          1. 20.2.5.1.1 DMA Receive Mode
          2. 20.2.5.1.2 DMA Transmit Mode
      6. 20.2.6  Buffer Management
        1. 20.2.6.1 Data Buffer
          1. 20.2.6.1.1 Memory Size and Block Length
          2. 20.2.6.1.2 Data Buffer Status
      7. 20.2.7  Transfer Process
        1. 20.2.7.1 Different Types of Commands
        2. 20.2.7.2 Different Types of Responses
      8. 20.2.8  Transfer or Command Status and Error Reporting
        1. 20.2.8.1 Busy Timeout for R1b, R5b Response Type
        2. 20.2.8.2 Busy Timeout After Write CRC Status
        3. 20.2.8.3 Write CRC Status Timeout
        4. 20.2.8.4 Read Data Timeout
      9. 20.2.9  Auto Command 12 Timings
        1. 20.2.9.1 Auto Command 12 Timings During Write Transfer
        2. 20.2.9.2 Auto Command 12 Timings During Read Transfer
      10. 20.2.10 Transfer Stop
      11. 20.2.11 Output Signals Generation
        1. 20.2.11.1 Generation on Falling Edge of SDMMC Clock
        2. 20.2.11.2 Generation on Rising Edge of SDMMC Clock
      12. 20.2.12 Test Registers
      13. 20.2.13 SDMMC Hardware Status Features
    3. 20.3 Low-Level Programming Models
      1. 20.3.1 SDMMC Initialization Flow
        1. 20.3.1.1 Enable OCP and CLKADPI Clocks
        2. 20.3.1.2 SD Soft Reset Flow
        3. 20.3.1.3 Set SD Default Capabilities
        4. 20.3.1.4 SDMMC Host and Bus Configuration
      2. 20.3.2 Operational Modes Configuration
        1. 20.3.2.1 Basic Operations for SDMMC
        2. 20.3.2.2 Card Detection, Identification, and Selection
    4. 20.4 SDMMC Registers
  22. 21Secure Digital Input/Output (SDIO)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 SDIO Interface Description
      2. 21.3.2 Protocol and Data Format
      3. 21.3.3 I/O Read/Write Command
        1. 21.3.3.1 IO_WR_DIRECT Command (CMD52)
        2. 21.3.3.2 IO_WR_EXTENDED Command (CMD53)
      4. 21.3.4 Reset
      5. 21.3.5 FIFO Operation
        1. 21.3.5.1 Rx FIFO (For Host Write)
        2. 21.3.5.2 Tx FIFO (For Host Read)
      6. 21.3.6 Interrupt Request
        1. 21.3.6.1 External Host IRQ
        2. 21.3.6.2 M33 IRQ
      7. 21.3.7 Transaction Details
        1. 21.3.7.1 Host write to SDIO IP (Rx FIFO)
          1. 21.3.7.1.1 Host write to SDIO IP (Rx FIFO) – Long SW latency case
          2. 21.3.7.1.2 Host write to SDIO IP (Rx FIFO) – CRC Error Case
        2. 21.3.7.2 Host reads from SDIO (TX buffer)
    4. 21.4 SDIO_CORE Registers
    5. 21.5 SDIO_CARD_FN1 Registers
  23. 22Inter-Integrated Circuit Sound (I2S)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  Signal Descriptions
    4. 22.4  Functional Description
      1. 22.4.1 Pin Configuration
      2. 22.4.2 Serial Format Configuration
        1. 22.4.2.1 Register Configuration
      3. 22.4.3 Left-Justified (LJF)
        1. 22.4.3.1 Register Configuration
      4. 22.4.4 Right-Justified (RJF)
        1. 22.4.4.1 Register Configuration
      5. 22.4.5 DSP
        1. 22.4.5.1 Register Configuration
      6. 22.4.6 Clock Configuration
    5. 22.5  Memory Interface
      1. 22.5.1 Sample Word Length
      2. 22.5.2 Padding Mechanism
      3. 22.5.3 Channel Mapping
      4. 22.5.4 Sample Storage in Memory
      5. 22.5.5 DMA Operation
        1. 22.5.5.1 Start-Up
        2. 22.5.5.2 Operation
        3. 22.5.5.3 Shutdown
    6. 22.6  Samplestamp Generator
      1. 22.6.1 Samplestamp Counters
      2. 22.6.2 Start-Up Triggers
      3. 22.6.3 Samplestamp Capture
      4. 22.6.4 Achieving constant audio latency
    7. 22.7  Error Detection
    8. 22.8  Usage
      1. 22.8.1 Start-Up Sequence
      2. 22.8.2 Shutdown Sequence
    9. 22.9  I2S Configuration Guideline
    10. 22.10 I2S Registers
  24. 23Pulse Density Modulation (PDM)
    1. 23.1  Introduction
    2. 23.2  Block Diagram
    3. 23.3  Input Selection
      1. 23.3.1 PDM Data Mode
      2. 23.3.2 Manchester Input Mode
    4. 23.4  CIC Filter
      1. 23.4.1 Filter Design
      2. 23.4.2 Digital Filter Output
      3. 23.4.3 Offset Binary Mode
      4. 23.4.4 Twos-Complement Mode
    5. 23.5  FIFO Organization in Different Modes
      1. 23.5.1 Single Mono Microphone Configuration
        1. 23.5.1.1 24-bit Sample Size
          1. 23.5.1.1.1 32-bit Data Read
        2. 23.5.1.2 16-bit Sample Size
          1. 23.5.1.2.1 32-bit Data Read
          2. 23.5.1.2.2 16-bit Data Read
        3. 23.5.1.3 8-bit Sample Size
          1. 23.5.1.3.1 32-bit Data Read
          2. 23.5.1.3.2 16-bit Data Read
          3. 23.5.1.3.3 8-bit Data Read
      2. 23.5.2 Stereo or Dual Mono Microphone Configuration
        1. 23.5.2.1 24-bit Sample Size
          1. 23.5.2.1.1 32-bit Data Read
        2. 23.5.2.2 16-bit Sample Size
          1. 23.5.2.2.1 32-bit Data Read
          2. 23.5.2.2.2 16-bit Data Read
        3. 23.5.2.3 8-bit Sample Size
          1. 23.5.2.3.1 32-bit Data Read
          2. 23.5.2.3.2 16-bit Data Read
          3. 23.5.2.3.3 8-bit Data Read
      3. 23.5.3 FIFO Threshold Setting
      4. 23.5.4 Reset FIFO
    6. 23.6  Automatic Gain Control (AGC)
      1. 23.6.1 Operation in 2's Complement Format
      2. 23.6.2 Operation in Offset Binary Format
    7. 23.7  Interrupts
    8. 23.8  Clock Select and Control
    9. 23.9  DMA Operation
    10. 23.10 Samplestamp Generator
      1. 23.10.1 Samplestamp Counters
      2. 23.10.2 Start-Up Triggers
      3. 23.10.3 Samplestamp Capture
      4. 23.10.4 Achieving Constant Audio Latency
    11. 23.11 Debug‑Mode Flag Behavior
    12. 23.12 Software Guidelines
    13. 23.13 PDM Registers
  25. 24Analog to Digital Converter (ADC)
    1. 24.1 Overview
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1  ADC Core
      2. 24.3.2  Voltage Reference Options
      3. 24.3.3  Internal Channels
      4. 24.3.4  Resolution Modes
      5. 24.3.5  ADC Clocking
      6. 24.3.6  Power Down Behavior
      7. 24.3.7  Sampling Trigger Sources and Sampling Modes
        1. 24.3.7.1 AUTO Sampling Mode
        2. 24.3.7.2 MANUAL Sampling Mode
      8. 24.3.8  Sampling Period
      9. 24.3.9  Conversion Modes
      10. 24.3.10 ADC Data Format
      11. 24.3.11 Status Register
      12. 24.3.12 ADC Events
        1. 24.3.12.1 Generic Event Publishers (INT_EVENT0 & INT_EVENT1)
        2. 24.3.12.2 DMA Trigger Event Publisher (INT_EVENT2)
        3. 24.3.12.3 Generic Event Subscriber
      13. 24.3.13 Advanced Features
        1. 24.3.13.1 Window Comparator
        2. 24.3.13.2 DMA & FIFO Operation
          1. 24.3.13.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
          2. 24.3.13.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
          3. 24.3.13.2.3 DMA/CPU Operation Summary Matrix
        3. 24.3.13.3 Ad-hoc Single Conversion
    4. 24.4 ADC Registers
  26. 25Controller Area Network (CAN)
    1. 25.1 Introduction
    2. 25.2 Functions
    3. 25.3 DCAN Subsystem
    4. 25.4 DCAN Functional Description
      1. 25.4.1 Operating Modes
        1. 25.4.1.1 Software Initialization
        2. 25.4.1.2 Normal Operation
        3. 25.4.1.3 Restricted Operation Mode
        4. 25.4.1.4 Bus Monitoring Mode
        5. 25.4.1.5 Disabled Automatic Retransmission
          1. 25.4.1.5.1 Frame Transmission in DAR Mode
        6. 25.4.1.6 Power Down (Sleep Mode)
          1. 25.4.1.6.1 DCAN clock stop and wake operations
          2. 25.4.1.6.2 DCAN debug suspend operation
        7. 25.4.1.7 Test Modes
          1. 25.4.1.7.1 External Loop Back Mode
          2. 25.4.1.7.2 Internal Loop Back Mode
      2. 25.4.2 Timestamp Generation
        1. 25.4.2.1 Block Diagram
      3. 25.4.3 Timeout Counter
      4. 25.4.4 Rx Handling
        1. 25.4.4.1 Acceptance Filtering
          1. 25.4.4.1.1 Range Filter
          2. 25.4.4.1.2 Filter for specific IDs
          3. 25.4.4.1.3 Classic Bit Mask Filter
          4. 25.4.4.1.4 Standard Message ID Filtering
          5. 25.4.4.1.5 Extended Message ID Filtering
        2. 25.4.4.2 Rx FIFOs
          1. 25.4.4.2.1 Rx FIFO Blocking Mode
          2. 25.4.4.2.2 Rx FIFO Overwrite Mode
        3. 25.4.4.3 Dedicated Rx Buffers
          1. 25.4.4.3.1 Rx Buffer Handling
        4. 25.4.4.4 Debug on CAN Support
          1. 25.4.4.4.1 Filtering for Debug Messages
          2. 25.4.4.4.2 Debug Message Handling
      5. 25.4.5 Tx Handling
        1. 25.4.5.1 Transmit Pause
        2. 25.4.5.2 Dedicated Tx Buffers
        3. 25.4.5.3 Tx FIFO
        4. 25.4.5.4 Tx Queue
        5. 25.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 25.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 25.4.5.7 Transmit Cancellation
        8. 25.4.5.8 Tx Event Handling
      6. 25.4.6 FIFO Acknowledge Handling
      7. 25.4.7 DCAN Message RAM
        1. 25.4.7.1 Message RAM Configuration
        2. 25.4.7.2 Rx Buffer and FIFO Element
        3. 25.4.7.3 Tx Buffer Element
        4. 25.4.7.4 Tx Event FIFO Element
        5. 25.4.7.5 Standard Message ID Filter Element
        6. 25.4.7.6 Extended Message ID Filter Element
      8. 25.4.8 Interrupt Requests
    5. 25.5 DCAN Wrapper
    6. 25.6 DCAN Clock Enable
    7. 25.7 DCAN Registers
  27. 26Revision History

17.7 UART Registers

Table 17-2 lists the memory-mapped registers for the UART registers. All register offset addresses not listed in Table 17-2 should be considered as reserved locations and the register contents should not be modified.

Table 17-2 UART Registers
OffsetAcronymRegister NameSection
0hDATAData RegisterSection 17.7.1
4hRXSTATReceive Status RegisterSection 17.7.2
18hFLAGStatus FlagsSection 17.7.3
20hLPWRDIVIrDA Low-Power CounterSection 17.7.4
24hIBRDInteger Baudrate DivisorSection 17.7.5
28hFBRDFractional Baudrate DividerSection 17.7.6
2ChLINECONLine ControlSection 17.7.7
30hUARTCTLOperation ControlSection 17.7.8
34hFIFOLEVFIFO Level SelectSection 17.7.9
38hIMASKInterrupt Mask ControlSection 17.7.10
3ChRISSTATRaw Interrupt StatusSection 17.7.11
40hMISMasked Interrupt StatusSection 17.7.12
44hICLRInterrupt ClearSection 17.7.13
48hDMACTLDMA ControlSection 17.7.14
FE0hPERID0Peripheral Identifier 0Section 17.7.15
FE4hPERID1Peripheral Identification 1Section 17.7.16
FE8hPERID2Peripheral Identification 2Section 17.7.17
FEChPERID3Peripheral Identification 3Section 17.7.18
FF0hCELLID0Cell Identification RegisterSection 17.7.19
FF4hCELLID1Cell Identification RegisterSection 17.7.20
FF8hCELLID2Cell Identification RegisterSection 17.7.21
FFChCELLID3Cell Identification RegisterSection 17.7.22
1000hCLKCTLClock ConfigurationSection 17.7.23

Complex bit access types are encoded to fit into small table cells. Table 17-3 shows the codes that are used for access types in this section.

Table 17-3 UART Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

17.7.1 DATA Register (Offset = 0h) [Reset = 00000000h]

DATA is shown in Table 17-4.

Return to the Summary Table.

Data Register (DATA) This register serves as the data interface for UART transmission and reception operations. Transmit Operation: - When FIFOs are enabled (FIFO EN = 1): Data written to this register is pushed onto the transmit First-In-First-Out (FIFO) buffer. - When FIFOs are disabled (FIFO EN = 0): Data is stored in the transmitter holding register (the bottom word of the transmit FIFO). Writing to this register automatically initiates data transmission from the Universal Asynchronous Receiver/Transmitter (UART). The data byte is formatted with a start bit, the appropriate parity bit (if parity is enabled), and a stop bit before transmission. Receive Operation: - When FIFOs are enabled: The data byte along with 4-bit status information (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO. - When FIFOs are disabled: The data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). To read received data, perform reads from this register. This operation provides both the data byte and corresponding status information. Status information can also be accessed separately through the RSR register.

Table 17-4 DATA Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11OVRERRR0hUART Overrun Error: This read-only bit indicates whether a data overrun error has occurred. When set to 1, it indicates that new data was received while the receive First-In-First-Out (FIFO) buffer was already full. The existing FIFO contents remain valid because no additional data is written to a full FIFO; only the contents of the shift register are overwritten. The bit automatically clears to 0 when space becomes available in the FIFO, allowing a new character to be written to it.
10BRKERRR0hBreak Error: This read-only bit indicates whether a break condition was detected on the UART receive line. When set to 1, it signals that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (including start bit, data bits, parity bit, and stop bits). In FIFO (First-In-First-Out) mode, this error is associated with the character at the top of the FIFO (the oldest received data character since the last read operation). When a break condition occurs, a null character (0x00) is automatically loaded into the FIFO. Normal character reception resumes after the receive data input (UARTRXD input pin) returns to a logical 1 (marking state) and the next valid start bit is detected.
9PERERRR0hParity Error (PE): Indicates a parity error in received data. When set to 1, the parity of the received data character does not match the expected parity as configured by the Line Control Register High (LCRH) fields for Even Parity Select (EPS) and Stick Parity Select (SPS). In First-In-First-Out (FIFO) mode, this error is associated with the character at the top of the FIFO (the oldest received data character since the last read operation). This read-only bit serves as an indicator for data integrity issues during transmission.
8FRMERRR0hUART Framing Error: This read-only bit indicates whether the received character has a valid stop bit (a valid stop bit is 1). When set to 1, a framing error has occurred, meaning the stop bit was invalid. In First-In-First-Out (FIFO) mode, this error is associated with the character at the top of the FIFO (the oldest received data character since the last read operation). The framing error typically indicates problems with clock synchronization between transmitter and receiver or incorrect baud rate settings.
7-0DATAR/W0hData Character [7:0]. This 8-bit field contains the data being transmitted or received. When writing to this field, the data character is pushed into the First-In-First-Out (FIFO) buffer for transmission. When reading from this field, the oldest received data character that has not yet been read is returned from the receive FIFO. Each read operation advances the FIFO pointer to the next available character.

17.7.2 RXSTAT Register (Offset = 4h) [Reset = 00000000h]

RXSTAT is shown in Table 17-5.

Return to the Summary Table.

Status This register is mapped to the same address as RXSTAT.* register. Reads from this address are associated with [RSR_ECR.*] register and return the receive status. Writes to this address are associated with RXSTAT.* register and clear the receive status flags (framing, parity, break, and overrun errors). If the status is read from this register, then the status information for break, framing and parity corresponds to the data character read from the Data Register, [DR.*] prior to reading the [RSR_ECR.*]. The status information for overrun is set immediately when an overrun condition occurs.

Table 17-5 RXSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3OVRERRR/W0hUART Overrun Error: This bit is set to 1 if data is received and the receive **FIFO** is already full. The **FIFO** contents remain valid because no more data is written when the **FIFO** is full, , only the contents of the shift register are overwritten. This is cleared to 0 once there is an empty space in the **FIFO** and a new character can be written to it.
  • 0h (R) = Error flag is not set
  • 0h (W) = Clears error flag if error is set. Write value is not important.
  • 1h (R) = Error flag is set
  • 1h (W) = Clears error flag if error is set. Write value is not important.
2BRKERRR/W0hUART Break Error: This bit is set to 1 if a break condition was detected, indicating that the received data input (**UARTRXD** input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). When a break occurs, a 0 character is loaded into the **FIFO**. The next character is enabled after the receive data input (**UARTRXD** input pin) goes to a 1 (marking state), and the next valid start bit is received.
  • 0h (W) = Clears error flag if error is set. Write value is not important.
  • 0h (R) = Error flag is not set
  • 1h (W) = Clears error flag if error is set. Write value is not important.
  • 1h (R) = Error flag is set
1PERERRR/W0hUART Parity Error: When set to 1, it indicates that the parity of the received data character does not match the parity that the EVPAR and STICKPAR select.
  • 0h (R) = Error flag is not set
  • 0h (W) = Clears error flag if error is set. Write value is not important.
  • 1h (R) = Error flag is set
  • 1h (W) = Clears error flag if error is set. Write value is not important.
0FRMERRR/W0hUART Framing Error: When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1).
  • 0h (R) = Error flag is not set
  • 0h (W) = Clears error flag if error is set. Write value is not important.
  • 1h (R) = Error flag is set
  • 1h (W) = Clears error flag if error is set. Write value is not important.

17.7.3 FLAG Register (Offset = 18h) [Reset = 00000000h]

FLAG is shown in Table 17-6.

Return to the Summary Table.

Status Flags Register (FLAG) This read-only register provides the current status of the Universal Asynchronous Receiver/Transmitter (UART) through various flags. These flags indicate the operational state of the UART, including buffer status, line conditions, and transmission states. Reading this register allows software to monitor UART status without affecting ongoing operations.

Table 17-6 FLAG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7TXEMPTYR1hUART Transmit FIFO Empty: This read-only bit indicates the empty status of the transmitter. The meaning of this bit depends on the state of the FIFO Enable bit (LCRH.FEN): - If the FIFO is disabled (LCRH.FEN = 0), this bit is set when the transmit holding register is empty. - If the FIFO is enabled (LCRH.FEN = 1), this bit is set when the transmit FIFO is empty. Note: This bit does not indicate if there is data in the transmit shift register, which may still be sending data when this bit is set.
6RXFULLR0hUART Receive First-In-First-Out (FIFO) Full. This read-only bit indicates whether the receive buffer is at capacity. The behavior of this bit depends on the state of the FIFO Enable (FEN) bit in the Line Control Register (LCRH): - When FIFO is disabled (LCRH.FEN = 0): This bit is set to 1 when the receive holding register contains data and cannot accept additional incoming data. - When FIFO is enabled (LCRH.FEN = 1): This bit is set to 1 when the receive FIFO buffer is completely full and cannot store additional bytes. This status bit can be used to prevent data loss by indicating when the receiver cannot accept more data.
5TXFULLR0hUART Transmit First-In-First-Out (FIFO) Full: This read-only bit indicates whether the transmit buffer is full. The specific behavior depends on the FIFO enable setting in the Line Control Register (LCRH.FEN): - When FIFO is disabled: This bit is set to 1 when the transmit holding register is full, indicating that no more data can be written until space becomes available. - When FIFO is enabled: This bit is set to 1 when the transmit FIFO buffer is completely full, indicating that no more data can be written until at least one byte has been transmitted. When this bit is set, attempts to write to the transmit buffer will result in data loss.
4RXEMPTYR1hUART Receive FIFO Empty (RXFE): This read-only bit indicates whether the receive First-In-First-Out (FIFO) buffer is empty. The interpretation of this bit depends on the FIFO Enable (FEN) setting in the Line Control Register (LCRH): - When FIFO is disabled (LCRH.FEN = 0): This bit is set to 1 when the receive holding register is empty. - When FIFO is enabled (LCRH.FEN = 1): This bit is set to 1 when the receive FIFO buffer is empty. When RXFE = 1, no more data is available to read. When RXFE = 0, at least one data entry is present in the receive buffer.
3TXBUSYR0hUART Busy (Transmitter Active): This read-only bit indicates whether the Universal Asynchronous Receiver/Transmitter (UART) is actively transmitting data. When set to 1, the UART is busy sending data through the transmission line. The bit remains set until the complete byte, including all stop bits, has been transmitted from the shift register. This bit is automatically set as soon as the transmit First-In-First-Out (FIFO) buffer becomes non-empty, regardless of whether the UART is enabled or disabled.
2-1RESERVEDR0hReserved
0CLEAR TO SENDR0hClear To Send (CTS): This read-only bit indicates the status of the active-low CTS input pin on the Universal Asynchronous Receiver/Transmitter (UART). When the CTS input pin is in a LOW state, this bit reads as 1. Conversely, when the CTS input pin is in a HIGH state, this bit reads as 0. This field allows software to monitor the hardware flow control signal status without directly accessing the pin.

17.7.4 LPWRDIV Register (Offset = 20h) [Reset = 00000000h]

LPWRDIV is shown in Table 17-7.

Return to the Summary Table.

The IrDA Low-Power Counter Register (LPWRDIV) configures the divisor values used in the IrDA low-power mode. This 32-bit read-write register determines the pulse width duration when the UART is operating in IrDA low-power mode. The programmed value in this register sets the division factor for the low-power infrared transmissions, allowing the system to meet the IrDA SIR low-power specification timing requirements.

Table 17-7 LPWRDIV Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0LPDIVR/W0hLow Power Divisor (ILPDVSR) - An 8-bit value that determines the baud rate divisor for the UART when operating in low-power mode. This field configures the frequency division applied to the UART clock source, allowing for power optimization while maintaining communication at reduced rates. Writing to this field updates the divisor value immediately.

17.7.5 IBRD Register (Offset = 24h) [Reset = 00000000h]

IBRD is shown in Table 17-8.

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Integer Baud-Rate Divisor Register (IBRD) This register contains the integer portion of the baud-rate divisor value used to establish the UART communication speed. The baud-rate is calculated using the following formula: Baud Rate = UARTCLK / (16 x (IBRD + (FBRD/64))) When this register is modified while transmission or reception is in progress, the new baud-rate value will not take effect until the current character transmission or reception is complete. This prevents communication errors during active data transfer. Address offset: 0x36 Size: 32 bits Access: Read-Write

Table 17-8 IBRD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0INTEGER DIVISORR/W0hInteger Baud Rate Divisor This 16-bit field specifies the integer component of the baud rate divisor used to configure the UART communication speed. The baud rate divisor is calculated using the following formula: Baud rate divisor = (UART reference clock frequency) / (16 x Baud rate) The valid range for the integer divisor is 1 to 65535. Setting INTEGER DIVISOR to 0 does not produce a valid baud rate. Additionally, if INTEGER DIVISOR is set to 0xFFFF, any non-zero values in the fractional baud rate divisor field FRAC will result in an invalid configuration. You must program a valid value to this field before performing any UART (Universal Asynchronous Receiver/Transmitter) receive (RX) or transmit (TX) operations.

17.7.6 FBRD Register (Offset = 28h) [Reset = 00000000h]

FBRD is shown in Table 17-9.

Return to the Summary Table.

Fractional Baud-Rate Divisor Register This register stores the fractional part of the baud-rate divisor value. Together with the integer part (stored in the IBRD register), it determines the UART baud rate. The fractional divisor is calculated as a 6-bit value (0-63) that represents m/64 where m is the fractional part. Important: If this register is modified while transmission or reception is ongoing, the baud rate will not be updated until the current character's transmission or reception is complete. This prevents data corruption during active communications. The FBRD register must be accessed using 32-bit word operations.

Table 17-9 FBRD Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0FRACR/W0hFractional Baud-Rate Divisor: This 6-bit field contains the fractional component of the baud rate divisor value. The complete baud rate divisor is calculated using the formula: Baud rate divisor = (UART reference clock frequency) / (16 x Baud rate) The divisor consists of an integer part (stored in IBRD.DIVINT) and this fractional part. The divisor must be between 1 and 65535 to be valid. Note that setting IBRD.DIVINT to 0 results in an invalid baud rate. Similarly, if IBRD.DIVINT is set to 0xFFFF, any non-zero values in DIVFRAC would create an invalid value exceeding the maximum. A valid value must be written to this field before the Universal Asynchronous Receiver/Transmitter (UART) can be used for receiving (RX) or transmitting (TX) operations.

17.7.7 LINECON Register (Offset = 2Ch) [Reset = 00000000h]

LINECON is shown in Table 17-10.

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Line Control Register (LINECON) - Controls UART line parameters including word length, parity, stop bits, and FIFO operation. This register configures the serial communication format and enables or disables the transmit and receive FIFOs. Settings in this register determine how data is framed during transmission and how it should be interpreted during reception.

Table 17-10 LINECON Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10-9DELIMLENR/W1hDelimiter Length. This field defines the length of the delimiter field that must be transmitted in UART Local Interconnect Network (LIN) mode. The value in this field determines the number of bits used for the delimiter in LIN communication.
  • 0h = 0
  • 1h = 1
  • 2h = 2
  • 3h = 3
8BRKSYNCR/W0hTransmit Break Synchronization (TXBRKSYNC): Controls the transmission of synchronization field in Local Interconnect Network (LIN) mode. 0: Synchronization field will not be transmitted in LIN mode. 1: Synchronization field will be transmitted in LIN mode and this bit will be automatically reset after transmission. Note: This functionality is only effective when parity is enabled via the PEN bit. When parity checking is disabled, this bit has no effect on UART operation.
7STICKPARR/W0hStick Parity Select: Controls whether the UART uses stick parity mode. 0: Stick parity is disabled 1: Stick parity is enabled. The parity bit is transmitted and checked as the inverse of the Even Parity Select (EPS) field value. When EPS=0, the parity bit is fixed at 1; when EPS=1, the parity bit is fixed at 0. Note: This bit has no effect when the Parity Enable (PEN) bit is set to 0, which disables all parity checking and generation.
6-5WORDLENR/W0hUART Word Length: These bits define the number of data bits transmitted or received in each frame. The WLEN field allows configuration of the data word size according to the following values: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits (default)
  • 0h = Word Length 5 bits
  • 1h = Word Length 6 bits
  • 2h = Word Length 7 bits
  • 3h = Word Length 8 bits
4FIFO ENR/W0hFIFO Enable. This bit enables the transmit and receive FIFOs (First-In-First-Out buffers). When set to 1, the FIFOs are enabled. When set to 0, the FIFOs are disabled, and the UART operates in character mode where only the transmitter holding register and receiver buffer register are used. For normal operation, this bit should be set to 1.
  • 0h = **FIFO**s are disabled (character mode) that is, the **FIFO**s become 1-byte-deep holding registers.
  • 1h = Transmit and receive **FIFO** buffers are enabled (**FIFO** mode)
3TWOSTBITR/W0hTwo Stop Bits Select (STP2): When set to 1, the UART transmits two stop bits at the end of each frame instead of the standard single stop bit. When cleared to 0, the UART transmits one stop bit. Note that the receive logic does not verify the presence of two stop bits, regardless of this setting.
2EVPARR/W0hEven Parity Select. When set to 1, even parity generation and checking is enabled. When cleared to 0, odd parity is selected if the Parity Enable (PEN) bit is set. This bit has no effect when the PEN bit is cleared.
  • 0h = Odd parity: The **UART** generates or checks for an odd number of 1s in the data and parity bits.
  • 1h = Even parity: The **UART** generates or checks for an even number of 1s in the data and parity bits.
1PARENR/W0hParity Enable. When set to 1, this bit enables parity checking and generation during UART data transmission and reception. When cleared to 0, parity checking and generation are disabled. The type of parity used (odd, even, stick) is controlled by the EPS and SPS bits in this register.
  • 0h = Parity is disabled and no parity bit is added to the data frame
  • 1h = Parity checking and generation is enabled.
0SBRKR/W0hUART Send Break. When this bit is set to 1, the UARTTXD output pin is driven to a low-level continuously after completing the transmission of the current character. For the proper execution of the break command, software must maintain this bit at 1 for at least two complete frames. For normal UART operation, this bit must be cleared to 0. This feature is typically used to signal line breaks in serial communication protocols.

17.7.8 UARTCTL Register (Offset = 30h) [Reset = 00000000h]

UARTCTL is shown in Table 17-11.

Return to the Summary Table.

Control Register (UARTCTL) - This register controls the operation of the hardware module. It contains configuration bits that determine the operational behavior and features of the device. The CTL register allows users to enable or disable functionality, select operating modes, and configure runtime parameters. Changes to this register take effect immediately unless otherwise specified by individual field descriptions.

Table 17-11 UARTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15CTS ENR/W0hClear To Send (CTS) hardware flow control enable. When set to 1, this bit enables the CTS hardware flow control mechanism, allowing the peripheral to pause transmission when the CTS signal indicates the receiver is not ready. When cleared to 0, CTS hardware flow control is disabled, and the peripheral ignores the CTS input signal during data transmission.
  • 0h = **CTS** hardware flow control disabled
  • 1h = **CTS** hardware flow control enabled
14RTSFLWR/W0hReady-to-Send (RTS) Hardware Flow Control Enable. When set to 1, this bit enables the RTS hardware flow control mechanism. When enabled, the UART asserts the RTS output signal when ready to receive data, and de-asserts it when the receive FIFO reaches the programmed threshold. When cleared to 0, RTS hardware flow control is disabled.
  • 0h = **RTS** hardware flow control disabled
  • 1h = **RTS** hardware flow control enabled
13-12RESERVEDR0hReserved
11RTSENR/W0hRequest To Send (RTS) - Controls the UART RTS (Request To Send) hardware flow control signal. When this bit is set to 1, the RTS output pin is driven LOW (active). When cleared to 0, the RTS output pin is driven HIGH (inactive). This bit directly controls the polarity of the external RTS signal used for hardware flow control to indicate to a connected device whether the UART is ready to receive data.
10RESERVEDR0hReserved
9RXENR/W1hUART Receive Enable. When set to 1, this bit enables the receiver functionality of the UART. If the UART receiver is disabled during an active reception by clearing this bit, the current character will be completely received before the receiver stops operation. This allows for graceful disabling of the receiver without data loss.
  • 0h = UART Receive disabled
  • 1h = UART Receive enabled
8TXENR/W1hTransmit Enable. When set, this bit enables the Universal Asynchronous Receiver/Transmitter (UART) transmission capability. When cleared, it disables transmission. If the UART is disabled during an active transmission, the hardware will complete the current character being transmitted before stopping the transmitter operation. This ensures that no partial characters are sent.
  • 0h = UART Transmit disabled
  • 1h = UART Transmit enabled
7LPBACKR/W0hLoop Back Enable: When set to 1, enables the UART loopback mode. In this mode, the UART Transmit Data (UARTTXD) output is internally connected to the UART Receive Data (UARTRXD) input, creating a closed testing circuit. This allows the transmission of data to be verified without external connections. When cleared to 0, the UART operates in normal mode with standard input/output paths.
  • 0h = Loop Back disabled
  • 1h = Loop Back enabled
6FIFOCNTR/W0hUART FIFO Concatenation Enable. When this bit is set, the FIFO (First-In-First-Out) concatenation feature is enabled in transmit (TX) mode, effectively doubling the transmit buffer capacity to 16 entries. This allows for more efficient data transmission by reducing the frequency of buffer empty conditions.
  • 0h = UART FIFO Concatenation disabled
  • 1h = UART FIFO Concatenation enabled
5DORMR/W0hDORMEN bit is only functionally makes sense for LIN mode of operation. When dormant mode is disabled, break and sync data shall be loaded to RX FIFO and associated interrupt flags shall be set as in normal UART operation. When dormant mode is enabled, break and sync data shall not be loaded to RX FIFO and RX FIFO shall be updated with actual data (PID) only after successful reception of break/sync fields.
  • 0h = 0
  • 1h = 1
4AUTBDENR/W0hAuto Baud Detection Enable. This bit enables or disables the automatic baud rate detection feature in Line Interface Network (LIN) mode. When set to 1, the controller automatically detects the baud rate from the incoming data stream. When cleared to 0, automatic baud rate detection is disabled and the baud rate must be manually configured.
  • 0h = 0
  • 1h = 1
3LINR/W0hLIN Mode Enable. This bit configures the module to operate in Local Interconnect Network (LIN) mode. When set to 1, the module operates in LIN mode according to the LIN specification. When cleared to 0, the module operates in standard mode. This setting affects communication protocol parameters and timing characteristics.
  • 0h = 0
  • 1h = 1
2IR LP MODER/W0hIrDA Low Power Mode Enable. This bit selects the Infrared Data Association (IrDA) encoding mode. When set to 1, the transmitter and receiver operate in low power mode. When cleared to 0, the standard IrDA mode is used. Low power mode reduces power consumption but may affect communication range.
  • 0h = Low-level bits are transmitted as active high with a 3/16th period width,
  • 1h = Low-level bits are transmitted with a pulse width of 3 times the period of IrLPBaud16, regardless of the selected bit rate.
1IRDAR/W0hSerial Infrared (SIR) Enable. When set to 1, enables the IrDA SIR modulation/demodulation functionality for transmitting and receiving data. When cleared to 0, the SIR function is disabled. Note that this bit has no effect if the UART is disabled via the UARTEN bit. Both UARTEN and SIREN must be set to enable SIR operation.
  • 0h = IrDA SIR ENDEC is disabled
  • 1h = IrDA SIR ENDEC is enabled. Data is transmitted and received via nSIROUT and SIRIN.
0ENR/W0hUART Enable - Controls the operating state of the UART module. When set to 1, the UART is enabled and fully functional. When cleared to 0, the UART is disabled and enters a low-power state. All UART registers can still be accessed while the module is disabled, but the transmitter and receiver are inactive. The UART must be enabled before any data transmission or reception can occur.
  • 0h = UART disabled
  • 1h = UART enabled

17.7.9 FIFOLEV Register (Offset = 34h) [Reset = 00000000h]

FIFOLEV is shown in Table 17-12.

Return to the Summary Table.

Interrupt **FIFO** Level Select

Table 17-12 FIFOLEV Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-3RXFIFOLVR/W2hReceive interrupt **FIFO** level select: This field sets the trigger points for the receive interrupt. Values 0b101-0b111 are reserved.
  • 1h = Receive **FIFO** becomes >= 1/4 full
  • 2h = Receive **FIFO** becomes >= 1/2 full
  • 3h = Receive **FIFO** becomes >= 3/4 full
2-0TX FIFO LVLR/W2hTransmit interrupt **FIFO** level select: This field sets the trigger points for the transmit interrupt. Values 0b101-0b111 are reserved.
  • 1h = Transmit **FIFO** becomes <= 1/4 full
  • 2h = Transmit **FIFO** becomes <= 1/2 full
  • 3h = Transmit **FIFO** becomes <= 3/4 full

17.7.10 IMASK Register (Offset = 38h) [Reset = 00000000h]

IMASK is shown in Table 17-13.

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Interrupt Mask Set/Clear Register (IMASK) - This register controls which interrupts are enabled or inactive. When a bit is set to 1, the corresponding interrupt is enabled and can generate an interrupt request to the system. When a bit is set to 0, the corresponding interrupt is inactive and will not generate an interrupt request, although the interrupt status can still be read through the status registers. Writing to this register sets or clears individual mask bits based on the written value.

Table 17-13 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16LSYNCTOR/W0hLIN Synchronization Timeout Error Interrupt Mask. This bit controls whether the Local Interconnect Network (LIN) synchronization timeout error generates an interrupt. When set to 1, the LINSYNCTOE interrupt is unmasked, and its state will be reflected in the MIS.LINSYNCTOE register. When cleared to 0, the LINSYNCTOE interrupt is masked, preventing it from being reflected in MIS.LINSYNCTOE. Reading this bit returns the current mask state for the LINSYNCTOE interrupt.
15LINBTOER/W0hLIN Break Timeout Error Interrupt Mask. This bit controls the masking of the Linear Interface (LIN) Break Timeout Error interrupt. When read, it returns the current mask status for the UART's LINBRKTOE interrupt. Writing a 1 to this bit sets the interrupt mask, causing the interrupt state to be reflected in the MIS.LINBRKTOE register. Writing a 0 clears the mask, preventing the interrupt state from being reflected in MIS.LINBRKTOE. This allows software to selectively enable or disable interrupt generation for LIN break timeout error conditions.
14LBRKMR/W0hLIN Break Interrupt Mask. Controls whether a Local Interconnect Network (LIN) break field received or detected will generate an interrupt. When read, this bit returns the current mask state for the UART's LIN break interrupt. Writing a 1 enables the interrupt (the interrupt state will be reflected in MIS.LINBRK register field). Writing a 0 disables the interrupt (MIS.LINBRK will not reflect the interrupt state). When enabled, the interrupt is triggered when the UART detects a LIN break condition on the receive line.
13RXDMIMR/W0hReceive Direct Memory Access (DMA) Done Interrupt Mask. This bit controls whether the receive DMA completion interrupt is enabled. When set to 1, the RXDMADONE interrupt is unmasked, allowing its state to be reflected in the Masked Interrupt Status register (MIS.RXDMADONEMIS). When cleared to 0, the RXDMADONE interrupt is masked, preventing it from being reflected in MIS.RXDMADONEMIS. Reading this bit returns the current mask state for the receive DMA done interrupt.
12TXDMAIMR/W0hTransmit DMA Done Interrupt Mask. This bit controls whether the TXDMADONE interrupt is masked. When read, it returns the current mask state for the Transmit DMA Done interrupt. Writing a 1 enables the interrupt, causing its state to be reflected in the MIS.TXDMADONEMIS register. Writing a 0 disables the interrupt, preventing it from being reflected in MIS.TXDMADONEMIS. This interrupt is triggered when a DMA transfer to the transmit FIFO has completed.
11EOTIMR/W0hEnd of Transmission Interrupt Mask. Controls whether the End of Transmission (EoT) interrupt is enabled. When set to 1, the EoT interrupt is enabled, and its state will be reflected in the MIS.EOTMIS field of the Masked Interrupt Status Register. When cleared to 0, the EoT interrupt is disabled, and MIS.EOTMIS will not reflect the interrupt even if it occurs. Reading this bit returns the current mask state for the UART's EoT interrupt.
10OEIMR/W0hOverrun Error Interrupt Mask. This bit controls whether the overrun error interrupt is enabled or masked. When read, it returns the current mask state for the UART (Universal Asynchronous Receiver/Transmitter) overrun error interrupt. Writing 1 to this bit enables the interrupt (sets the mask), causing the interrupt state to be reflected in the MIS.OEMIS field of the Masked Interrupt Status Register. Writing 0 disables the interrupt (clears the mask), preventing the overrun error condition from generating an interrupt and MIS.OEMIS will not reflect the interrupt state.
9BRKERRIMR/W0hBreak Error Interrupt Mask. This bit controls whether break errors generate an interrupt. When set to 1, break error interrupts are enabled and their status will be reflected in the Break Error Masked Interrupt Status (MIS.BEMIS) bit. When cleared to 0, break error interrupts are masked, preventing them from being reflected in MIS.BEMIS. Reading this bit returns the current mask state for the Universal Asynchronous Receiver/Transmitter (UART) break error interrupt.
8PEERRMR/W0hParity Error Interrupt Mask. This bit controls whether parity errors generate an interrupt. When set to 1, the UART parity error interrupt is enabled, and parity error conditions will be reflected in the MIS.PEMIS (Masked Interrupt Status - Parity Error) bit. When cleared to 0, parity error interrupts are masked, preventing these conditions from being reflected in MIS.PEMIS. Reading this bit returns the current mask state for the UART's parity error interrupt.
7FEIMR/W0hFraming Error Interrupt Mask. This bit controls whether framing errors trigger an interrupt. When set to 1, the framing error interrupt is enabled, causing the interrupt status to be reflected in the Masked Interrupt Status register (MIS.FEMIS). When cleared to 0, framing error interrupts are masked and will not be reflected in MIS.FEMIS. Reading this bit returns the current mask state for the Universal Asynchronous Receiver/Transmitter (UART) framing error interrupt.
6RXTOUTR/W0hReceive Timeout Interrupt Mask. This bit controls the masking of the Universal Asynchronous Receiver/Transmitter (UART) receive timeout interrupt. When read, it returns the current mask state for the receive timeout interrupt. When written: - Writing 1: Enables the receive timeout interrupt. When enabled, the interrupt state will be reflected in the MIS.RTMIS register bit. - Writing 0: Disables the receive timeout interrupt, preventing it from being reflected in the interrupt status. Note: The raw interrupt status for receive timeout (RIS.RTRIS) can only be set when this mask is enabled (RTIM = 1). This behavior serves as a power-saving feature, as the interrupt detection logic remains inactive until masked. When the mask is enabled, the same interrupt status can be read from either MIS.RTMIS or RIS.RTRIS registers.
5TXINTR/W0hTransmit Interrupt Mask. Controls whether the transmit interrupt is masked. When this bit is set to 1, the transmit interrupt is unmasked, allowing the interrupt status to be reflected in the TXMIS bit of the Masked Interrupt Status (MIS) register. When cleared to 0, the transmit interrupt is masked, preventing it from being reflected in the MIS.TXMIS bit. Reading this bit returns the current mask state for the Universal Asynchronous Receiver/Transmitter (UART) transmit interrupt.
4RXINTR/W0hReceive Interrupt Mask. This bit controls whether the receive interrupt is enabled. When set to 1, the mask for the Universal Asynchronous Receiver/Transmitter (UART) receive interrupt is enabled, causing the interrupt state to be reflected in the Masked Interrupt Status register (MIS.RXMIS). When cleared to 0, the mask is disabled, preventing the receive interrupt from being reflected in MIS.RXMIS. Reading this bit returns the current mask status for the UART's receive interrupt.
3-2RESERVEDR0hReserved
1CTSMR/W0hClear To Send (CTS) modem interrupt mask. When set to 1, this bit enables the CTS modem interrupt, allowing the interrupt state to be reflected in the Masked Interrupt Status register (MIS.CTSMMIS). When cleared to 0, the CTS modem interrupt is masked, preventing it from being reflected in MIS.CTSMMIS. Reading this bit returns the current mask state for the UART's Clear To Send interrupt.
0RESERVEDR0hReserved

17.7.11 RISSTAT Register (Offset = 3Ch) [Reset = 00000000h]

RISSTAT is shown in Table 17-14.

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Raw Interrupt Status

Table 17-14 RISSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16LINTOESYR0hLIN SYNC field time out interrupt status: This field returns the raw interrupt state of whether sync field is measurable in UART's LIN mode of operation. This is set when the timer measuring the SYNC field overflows.
15LINBKTMOR0hLIN BRK field time out interrupt status: This field returns the raw interrupt state of whether break field is measurable in UART's LIN mode of operation. This is set when the timer measuring the Break field overflows.
14LINBRKR0hLIN BRK detected interrupt status: This field returns the raw interrupt state of whether break field is received/detected in UART's LIN mode of operation.
13RXDMADNR0hRx DMA done interrupt status: This field returns the raw interrupt state of UART's rx dma done interrupt. RX DMA done flag is set when you receive rx dma done status from dma module.
12DMADTXR0hTx DMA done interrupt status: This field returns the raw interrupt state of UART's tx dma done interrupt. TX DMA done flag is set when you receive tx dma done status from dma module.
11TXEOTR0hEnd of Transmission interrupt status: This field returns the raw interrupt state of UART's end of transmission interrupt. End of transmission flag is set when all the Transmit data in the FIFO and on the TX Line is transmitted.
10OVRNERRR0hOverrun error interrupt status: This field returns the raw interrupt state of **UART**'s overrun error interrupt. Overrun error occurs if data is received and the receive **FIFO** is full.
9BREAKR0hBreak error interrupt status: This field returns the raw interrupt state of **UART**'s break error interrupt. Break error is set when a break condition is detected, indicating that the received data input (**UARTRXD** input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits).
8PARITYR0hParity error interrupt status: This field returns the raw interrupt state of **UART**'s parity error interrupt. Parity error is set if the parity of the received data character does not match the parity that the EVPAR and STICKPAR select.
7FRMERRR0hFraming error interrupt status: This field returns the raw interrupt state of **UART**'s framing error interrupt. Framing error is set if the received character does not have a valid stop bit (a valid stop bit is 1).
6RXTOR0hReceive timeout interrupt status: This field returns the raw interrupt state of **UART**'s receive timeout interrupt. The receive timeout interrupt is asserted when the receive **FIFO** is not empty, and no more data is received during a 32-bit period. The receive timeout interrupt is cleared either when the **FIFO** becomes empty through reading all the data, or when a 1 is written to RTIC. The raw interrupt for receive timeout cannot be set unless the mask is set (RXTOUT = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from RTOUT and RXTO.
5TXRISR0hTransmit interrupt status: This field returns the raw interrupt state of **UART**'s transmit interrupt. When **FIFO**s are enabled (FIFO EN = 1), the transmit interrupt is asserted if the number of bytes in transmit **FIFO** is equal to or lower than the programmed trigger level (TX FIFO LVL). The transmit interrupt is cleared by writing data to the transmit **FIFO** until it becomes greater than the trigger level, or by clearing the interrupt through TXCLR. When **FIFO**s are disabled (FIFO EN = 0), that is they have a depth of one location, the transmit interrupt is asserted if there is no data present in the transmitters single location. It is cleared by performing a single write to the transmit **FIFO**, or by clearing the interrupt through TXCLR.
4RXINTR0hReceive interrupt status: This field returns the raw interrupt state of **UART**'s receive interrupt. When **FIFO**s are enabled (FIFO EN = 1), the receive interrupt is asserted if the receive **FIFO** reaches the programmed trigger level (RXFIFOLV). The receive interrupt is cleared by reading data from the receive **FIFO** until it becomes less than the trigger level, or by clearing the interrupt through RXICLR. When **FIFO**s are disabled (FIFO EN = 0), that is they have a depth of one location, the receive interrupt is asserted if data is received thereby filling the location. The receive interrupt is cleared by performing a single read of the receive **FIFO**, or by clearing the interrupt through RXICLR.
3-2RESERVEDR0hReserved
1CTSRISR0hClear to Send (CTS) modem interrupt status: This field returns the raw interrupt state of **UART**'s clear to send interrupt.
0RESERVEDR0hReserved

17.7.12 MIS Register (Offset = 40h) [Reset = 00000000h]

MIS is shown in Table 17-15.

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Masked Interrupt Status (MIS) Register. This read-only register contains the masked interrupt status flags. A set bit (1) indicates that the corresponding interrupt is active and enabled in the interrupt mask register. A cleared bit (0) indicates that either the interrupt is not active or it is disabled by the mask register. Reading this register provides immediate visibility of all interrupt conditions that can trigger an interrupt request to the processor.

Table 17-15 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16LINSYNCTOR0hLIN Synchronization Field Timeout Error Interrupt Status: This read-only bit returns the masked interrupt state of the Local Interconnect Network (LIN) synchronization field timeout error interrupt. The value is the logical AND of the raw interrupt state (RIS.LINSYNCTOERIS) and the interrupt mask setting (IMSC.LINSYNCTOEIM). When set to 1, it indicates that a masked LIN synchronization timeout error interrupt is active.
15LINBRKTOR0hLIN Break Field Timeout Error Interrupt Status: This read-only bit indicates the masked interrupt state of the Local Interconnect Network (LIN) Break Field timeout error. The value is determined by the logical AND of the raw interrupt state (RIS.LINBRKTOERIS) and the corresponding interrupt mask setting (IMSC.LINBRKTOEIM). When set to 1, it indicates that a masked LIN Break Field timeout error interrupt is active and requires service.
14BRKMR0hLocal Interconnect Network (LIN) Break Masked Interrupt Status. This read-only field indicates the masked interrupt status of the LIN break detection mechanism. A value of 1 indicates that a LIN break has been detected and the interrupt is enabled. This value represents the logical AND of the raw interrupt status (RIS.LINBRKRIS) and the interrupt mask setting (IMSC.LINBRKIM). When this field is set, it means a valid LIN break condition has been detected on the interface and requires software attention.
13DMARXDNR0hRx DMA done interrupt status: This field returns the masked interrupt state of the rx dma done interrupt which is the AND product of raw interrupt state RIS.RXDMADONERIS and the mask setting IMSC.RXDMADONEIM.
12TXDMAISR0hTransmit DMA Done Masked Interrupt Status: This read-only field indicates the masked interrupt status of the Transmit DMA Done interrupt. It returns the logical AND result of the raw interrupt state (RIS.TXDMADONERIS) and the interrupt mask setting (IMSC.TXDMADONEIM). When this bit is set to 1, it indicates that a Transmit DMA Done interrupt is both active and enabled.
11EOTTXMR0hEnd of Transmission (EOT) Interrupt Status: This read-only field indicates the masked interrupt state of the End of Transmission interrupt. It represents the logical AND of the raw interrupt state (RIS.EOTRIS) and the interrupt mask setting (IMSC.EOTIM). When this bit is set to 1, it indicates that a transmission has completed and the associated interrupt is both active and enabled. This status can be used to determine if an End of Transmission interrupt is pending service.
10OVRERRR0hOverrun Error Masked Interrupt Status: Indicates the masked interrupt status of the overrun error condition. This bit is the logical AND of the raw interrupt state (RIS.OERIS) and the interrupt mask setting (IMSC.OEIM). When this bit is set to 1, it indicates that an overrun error has occurred and the interrupt is not masked. Read-only.
9BERRR0hBreak Error Masked Interrupt Status: This read-only field indicates the current masked interrupt state of the break error interrupt. The value represents the logical AND of the raw break error interrupt state (BREAK) and the corresponding interrupt mask setting (BRKERRIM). When set to 1, it indicates that both a break error has been detected and its interrupt is enabled. When set to 0, either no break error has occurred or the break error interrupt is masked.
8PERRR0hParity Error Masked Interrupt Status: This read-only field indicates the current masked interrupt status of the parity error interrupt. It represents the logical AND between the raw interrupt state PARITY and the interrupt mask setting PEERRM. When this bit is set to 1, both a parity error has occurred and its interrupt is enabled. This field can be used to determine if a parity error is currently triggering an interrupt request to the system.
7FEERRR0hFraming Error Masked Interrupt Status: This read-only bit returns the masked interrupt state of the framing error interrupt. It represents the logical AND of the raw interrupt state FRMERR and the interrupt mask setting FEIM. When set to 1, it indicates that a framing error has occurred and the corresponding interrupt is enabled. This field can be used to determine if a framing error is contributing to an interrupt condition.
6RTOUTR0hReceive Timeout Masked Interrupt Status: This read-only bit returns the masked interrupt state of the receive timeout interrupt. The raw interrupt for receive timeout cannot be set unless the corresponding interrupt mask bit is enabled (RXTOUT = 1). This behavior is designed for power saving, as the mask functions as an enable control. As a result, the same status information can be read from both this bit (RTOUT) and the raw interrupt status bit (RXTO).
5TXISR0hTransmit Masked Interrupt Status: This read-only bit indicates the current state of the masked transmit interrupt. It represents the logical AND between the raw transmit interrupt status TXRIS and the transmit interrupt mask TXINT. When this bit is set to 1, it indicates that a transmit interrupt is both active and enabled. This field can be used to determine if a transmit interrupt is currently requesting service.
4RXISR0hMasked Receive Interrupt Status: This read-only field indicates the current status of the masked receive interrupt. It represents the logical AND operation between the raw receive interrupt state (RIS.RXRIS) and the receive interrupt mask setting (IMSC.RXIM). When this bit is set to 1, it indicates that both the raw receive interrupt is active and its corresponding mask is enabled, signaling that the interrupt requires service. When clear (0), either no receive interrupt is pending or the interrupt is masked.
3-2RESERVEDR0hReserved
1CTSMR0hClear to Send (CTS) Modem Masked Interrupt Status: This read-only field indicates the masked interrupt status of the Clear to Send modem interrupt. It represents the logical AND between the raw interrupt state CTSRIS and the interrupt mask setting CTSM. When this bit is set to 1, it indicates that a CTS interrupt is pending and has been enabled via the mask register. When set to 0, either no CTS interrupt is pending or the interrupt is disabled by the mask.
0RESERVEDR0hReserved

17.7.13 ICLR Register (Offset = 44h) [Reset = 00000000h]

ICLR is shown in Table 17-16.

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Interrupt Clear Register (ICLR) This write-only register clears specific interrupts. Writing a '1' to any bit position clears the corresponding interrupt. Writing a '0' to any bit position has no effect. After writing to this register, the corresponding interrupt status bits in the interrupt status register will be cleared, indicating that the interrupt has been acknowledged. Note: This is a write-only register and will return undefined values when read.

Table 17-16 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved
18-17RESERVEDR0hReserved
16SYNTOUTW0hLIN SYNC Timeout Interrupt Clear: Writing 1 to this field clears the Local Interconnect Network (LIN) synchronization timeout error interrupt (RIS.LINSYNCTOERIS). Writing 0 has no effect. This bit is write-only.
15LINBKTOCW0hLIN Break Timeout Error Interrupt Clear: Writing 1 to this bit clears the LIN Break Timeout Error interrupt (indicated by RIS.LINBRKTOERIS). Writing 0 has no effect. This bit is write-only and is used to acknowledge and clear the timeout condition that occurs when a LIN break field is detected.
14LINBRKW0hLIN Break Interrupt Clear: Writing 1 to this field clears the Linear Integrated Network (LIN) break field detected interrupt (RIS.LINBRKRIS). Writing 0 has no effect. This field allows software to acknowledge and clear a detected LIN break condition.
13RDMAICW0hReceive Direct Memory Access (DMA) Done Interrupt Clear: Writing 1 to this bit clears the Receive DMA Done interrupt status (indicated by RIS.RXDMADONERIS). Writing 0 to this bit has no effect. This field is write-only and is used to acknowledge and clear the interrupt after it has been serviced.
12TXDMAICW0hTransmit DMA Done Interrupt Clear: Writing 1 to this field clears the Transmit DMA Done interrupt (indicated by RIS.TXDMADONERIS). Writing 0 to this field has no effect. This write-only bit allows software to acknowledge and clear the interrupt after the DMA has completed a transmit operation.
11EOTCW0hEnd of Transmission (EOT) Interrupt Clear: Writing 1 to this field clears the End of Transmission interrupt flag (RIS.EOTRIS). Writing 0 to this field has no effect. This bit is write-only and is used to acknowledge and clear the EOT interrupt after the transmission has completed.
10OERCLRW0hOverrun Error Interrupt Clear: Writing 1 to this bit clears the overrun error interrupt flag (indicated by RIS.OERIS). Writing 0 has no effect. This field allows software to acknowledge and clear the overrun error condition after it has been handled.
9BEICW0hBreak Error Interrupt Clear: Writing 1 to this field clears the break error interrupt flag (indicated by the BERIS bit in the Raw Interrupt Status register). Writing 0 has no effect. This bit is write-only and is used to acknowledge and clear break error conditions detected by the hardware.
8PERICLRW0hParity Error Interrupt Clear: Writing a 1 to this bit clears the parity error interrupt flag (indicated by the PERIS bit in the Raw Interrupt Status register). Writing a 0 has no effect. This field is write-only and is used to acknowledge and clear parity error conditions detected by the hardware.
7FEICLRW0hFraming Error Interrupt Clear: Writing a 1 to this bit clears the Framing Error interrupt status bit (FRMERR). Writing a 0 has no effect. This bit is write-only and is used to acknowledge and clear the framing error condition after it has been detected and handled by software.
6RTICW0hReceive Timeout Interrupt Clear: Writing a 1 to this bit clears the receive timeout interrupt flag (indicated by RIS.RTRIS). Writing a 0 has no effect. This field is write-only and is used to acknowledge and clear receive timeout interrupt conditions.
5TXCLRW0hTransmit Interrupt Clear: Writing a 1 to this bit clears the transmit interrupt status flag (RIS.TXRIS). Writing a 0 has no effect. This write-only bit allows software to acknowledge and clear pending transmit interrupts.
4RXICLRW0hReceive Interrupt Clear: Writing a 1 to this field clears the receive interrupt status, as indicated in the Receive Interrupt Status bit (RXINT). Writing a 0 to this field has no effect. This write-only field provides a mechanism for acknowledging and clearing receive-related interrupt conditions.
3-2RESERVEDW0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Write 0
1CTSICW0hClear to Send (CTS) Modem Interrupt Clear: Writing 1 to this bit clears the CTS modem interrupt status indicated by the CTSRMIS bit in the Raw Interrupt Status (RIS) register. Writing 0 to this bit has no effect. This field is write-only and is used to acknowledge and clear pending CTS modem interrupts.
0RESERVEDW0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Write 0.

17.7.14 DMACTL Register (Offset = 48h) [Reset = 00000000h]

DMACTL is shown in Table 17-17.

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Direct Memory Access (DMACTL) Control Register. This register configures and controls the operation of the DMA controller, which enables high-speed data transfers between memory locations and peripherals without CPU intervention. The DMA controller can be configured to perform memory-to-memory, memory-to-peripheral, or peripheral-to-memory transfers, optimizing system performance by freeing the CPU for other tasks during data movement operations.

Table 17-17 DMACTL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2DMA ERRR/W0hDMA on Error. When set to 1, this bit disables the Direct Memory Access (DMA) receive request outputs (both single and burst requests) when a UART error interrupt is asserted. Specifically, the DMA is disabled when any of the following error interrupts occur: parity error PARITY, break error BREAK, framing error FRMERR, or overrun error OVRNERR. When cleared to 0, DMA receive requests continue to function regardless of UART errors.
1TX DMA ENR/W0hTransmit DMA Enable. When this bit is set to 1, Direct Memory Access (DMA) for the transmit First-In-First-Out (FIFO) buffer is enabled. This allows data transfers to occur between memory and the transmit FIFO without CPU intervention, improving data throughput and reducing processor overhead.
0RX DMA ENR/W0hReceive Direct Memory Access (DMA) Enable. When set to 1, this bit enables DMA operations for the receive First-In-First-Out (FIFO) buffer. When enabled, data transfers from the receive FIFO can occur without CPU intervention. When cleared to 0, DMA operations for the receive FIFO are disabled, and the CPU must handle data transfers.

17.7.15 PERID0 Register (Offset = FE0h) [Reset = 00000000h]

PERID0 is shown in Table 17-18.

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Peripheral Identification 0 Register . This read-only register contains the least significant byte of the peripheral identification code. It is part of the standard ARM peripheral identification registers that uniquely identify the peripheral. This register is primarily used during system initialization and debugging to confirm the peripheral type and version.

Table 17-18 PERID0 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0PARTR11hThe PARTNUMBER0 field contains bits 0-7 of the peripheral part number. This read-only field helps identify the specific peripheral device. It is used in conjunction with PARTNUMBER1 (in register PERIPHID1) to form the complete part number identification code.

17.7.16 PERID1 Register (Offset = FE4h) [Reset = 00000000h]

PERID1 is shown in Table 17-19.

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Peripheral Identification Register 1 contains bits 12:8 of the peripheral identification code. This read-only register is part of the standard ARM peripheral identification registers that help software identify the peripheral. It works together with other peripheral identification registers (PERIPHID0, PERIPHID2, PERIPHID3) to form a complete peripheral ID. The value stored in this register is fixed at manufacturing time and cannot be modified by software.

Table 17-19 PERID1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-4DESGNIDR1hDesigner Identification [4:7]. This read-only field identifies the designer of the peripheral, which in this case is ARM (Advanced RISC Machines). The field contains the upper four bits of the JEP-106 code that uniquely identifies ARM as the designer.
3-0PARTNUM1R0hIdentifies the peripheral

17.7.17 PERID2 Register (Offset = FE8h) [Reset = 00000000h]

PERID2 is shown in Table 17-20.

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Peripheral Identification 2 Register. This read-only register is part of the standard ARM peripheral identification register set. It contains the device revision number and the designer's JEP106 identification code for this peripheral. This information can be used for device detection, firmware compatibility verification, and hardware revision identification.

Table 17-20 PERID2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-4REVR3hRevision Number (REVISION): This read-only field contains the revision number of the UART peripheral. It identifies the specific version of the hardware implementation, allowing software to adapt to different hardware capabilities or behaviors between revisions.
3-0DESGN1R4hDesigner Identifier. This read-only field identifies the designer of the peripheral as ARM. The field occupies bits [3:0] of the Peripheral Identification Register 2 (PERIPHID2) and is hard-coded during manufacturing.

17.7.18 PERID3 Register (Offset = FECh) [Reset = 00000000h]

PERID3 is shown in Table 17-21.

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Peripheral Identification 3 Register contains component identification information defined by ARM. This read-only register is part of the standard peripheral identification registers that help software identify the peripheral. The register holds manufacturer-specific information and, along with other peripheral ID registers, forms the complete peripheral identification code. This register is located at offset 0x4076 and has a width of 32 bits.

Table 17-21 PERID3 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CONFIGR0hConfiguration Option [7:0] - This read-only field identifies the specific configuration option of the Universal Asynchronous Receiver/Transmitter (UART) peripheral. The value indicates the hardware implementation variant and features available in this UART instance.

17.7.19 CELLID0 Register (Offset = FF0h) [Reset = 00000000h]

CELLID0 is shown in Table 17-22.

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PrimeCell Identification Register 0 contains part of the fixed identification code (0x0000000D) that uniquely identifies this as an ARM PrimeCell component. This read-only register holds the least significant byte of the identification code and is used in conjunction with PCELLID1-3 registers for peripheral identification. Software can read this register to verify the presence and type of peripheral in the system.

Table 17-22 CELLID0 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0RESERVEDR0hReserved

17.7.20 CELLID1 Register (Offset = FF4h) [Reset = 00000000h]

CELLID1 is shown in Table 17-23.

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PrimeCell Identification Register 1 contains part of the standard ARM PrimeCell component identification code. This read-only register, located at offset 0x4084, contains the second byte of the 32-bit component identifier. It is typically used in conjunction with other component ID registers (PCELLID0, PCELLID2, and PCELLID3) for peripheral identification and discovery during system initialization.

Table 17-23 CELLID1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0RESERVEDR0hReserved

17.7.21 CELLID2 Register (Offset = FF8h) [Reset = 00000000h]

CELLID2 is shown in Table 17-24.

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PrimeCell Identification Register 2 contains part of the standard ARM PrimeCell identification code. This read-only register holds the second byte of the component identification code, providing information about the component type and features. This register, along with PCELLID0, PCELLID1, and PCELLID3, forms the complete PrimeCell identification signature that software can use to identify the peripheral.

Table 17-24 CELLID2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0RESERVEDR0hReserved

17.7.22 CELLID3 Register (Offset = FFCh) [Reset = 00000000h]

CELLID3 is shown in Table 17-25.

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PrimeCell Identification Register 3 contains the third byte of the component identification code. This read-only register is part of the CoreSight identification scheme that uniquely identifies this peripheral as a PrimeCell component. The register is located at offset 0x4092 and contains a fixed 32-bit value, though typically only the least significant byte is used. This register, along with PCELLID0-PCELLID2, forms the complete PrimeCell identification code that software can read to confirm the peripheral type during system initialization or debug.

Table 17-25 CELLID3 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0RESERVEDR0hReserved

17.7.23 CLKCTL Register (Offset = 1000h) [Reset = 00000000h]

CLKCTL is shown in Table 17-26.

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Clock Configuration Register. This register controls the activation and deactivation of the Universal Asynchronous Receiver/Transmitter with Local Interconnect Network (UART-LIN) bus clock. When activated, the clock signal is provided to the UART-LIN interface, allowing it to operate. When deactivated, the clock is stopped to reduce power consumption, which prevents any UART-LIN communication.

Table 17-26 CLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0CLKENR/W0hMemory Clock Enable. This bit enables or disables the bus clock for UART Linear Interface (Uartlin). When set to 1, the memory clock is enabled. When set to 0, the memory clock is disabled, which reduces power consumption but makes the UART Linear Interface inaccessible.
  • 0h = Disables the clock to *Uartlin*
  • 1h = Enables the clock to *Uartlin*