ADS61B29 12-Bit, 250-MSPS Analog-to-Digital Converter (ADC) |

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12-Bit, 250-MSPS Analog-to-Digital Converter (ADC)



The ADS61B49 (ADS61B29) is a 14-bit (12-bit) A/D converter with a sampling rate up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 48-QFN package. An integrated analog buffer makes it well-suited for multi-carrier, wide bandwidth communications applications. The buffer maintains constant performance and input impedance across a wide frequency range.

The ADS61B49 (ADS61B29) has fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both Double Data Rate (DDR) LVDS and parallel CMOS digital output interfaces are available. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.

It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (-40°C to 85°C).


  • Integrated High Impedance Analog Input Buffer
  • Maximum Sample Rate: 250 MSPS
  • 14-Bit Resolution — ADS61B49
  • 12-Bit Resolution — ADS61B29
  • 790 mW Total Power Dissipation at 250 MSPS
  • Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
  • Programmable Fine Gain up to 6 dB for SNR/SFDR Trade-Off and 1-Vpp Full-Scale Operation
  • DC Offset Correction
  • Supports Input Clock Amplitude Down to 400 mVPP Differential
  • 48-QFN Package (7mm × 7mm)
  • Pin Compatible with ADS6149 Family
    • Multicarrier, Wide Bandwidth Communications
    • Wireless Multi-Carrier Communications Infrastructure
    • Software Defined Radio
    • Power Amplifier Linearization Feedback ADC
    • 802.16d/e
    • Test and Measurement Instrumentation
    • High Definition Video
    • Medical Imaging
    • Radar Systems


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Part number Order Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADS61B29 Order now 250     High Performance     12     1     70.1     11.1     92     790     2     DDR LVDS
Parallel CMOS    
-40 to 85     700     Yes     VQFN | 48     48VQFN: 49 mm2: 7 x 7 (VQFN | 48)     Catalog     Pipeline    
ADS61B23 Samples not available 80     Low Power     12     1     70.2     11.3     87     351     2     DDR LVDS
Parallel CMOS    
-40 to 85     450     Yes     VQFN | 32     32VQFN: 25 mm2: 5 x 5 (VQFN | 32)     Catalog     Pipeline    
ADS61B49 Samples not available 250     High Performance     14     1     72.3     11.3     92     790     2     DDR LVDS
Parallel CMOS    
-40 to 85     700     Yes     VQFN | 48     48VQFN: 49 mm2: 7 x 7 (VQFN | 48)     Catalog     Pipeline