SPRSP65G April   2021  – May 2024 AM2431 , AM2432 , AM2434

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1. 5.1.1 AM243x ALV Pin Diagram
      2. 5.1.2 AM243x ALX Pin Diagram
    2. 5.2 Pin Attributes
      1.      13
      2.      14
      3. 5.2.1 AM243x Package Comparison Table (ALV vs. ALX)
    3. 5.3 Signal Descriptions
      1.      17
      2. 5.3.1  AM243x_ALX Package - Unsupported Interfaces and Signals
      3. 5.3.2  ADC
        1.       MAIN Domain Instances
          1.        21
      4. 5.3.3  CPSW
        1.       MAIN Domain Instances
          1.        24
          2.        25
          3.        26
          4.        27
          5. 5.3.3.1.1 CPSW3G IOSETs
      5. 5.3.4  CPTS
        1.       MAIN Domain Instances
          1.        31
          2.        32
      6. 5.3.5  DDRSS
        1.       MAIN Domain Instances
          1.        35
      7. 5.3.6  ECAP
        1.       MAIN Domain Instances
          1.        38
          2.        39
          3.        40
      8. 5.3.7  Emulation and Debug
        1.       MAIN Domain Instances
          1.        43
        2.       MCU Domain Instances
          1.        45
      9. 5.3.8  EPWM
        1.       MAIN Domain Instances
          1.        48
          2.        49
          3.        50
          4.        51
          5.        52
          6.        53
          7.        54
          8.        55
          9.        56
          10.        57
      10. 5.3.9  EQEP
        1.       MAIN Domain Instances
          1.        60
          2.        61
          3.        62
      11. 5.3.10 FSI
        1.       MAIN Domain Instances
          1.        65
          2.        66
          3.        67
          4.        68
          5.        69
          6.        70
          7.        71
          8.        72
      12. 5.3.11 GPIO
        1.       MAIN Domain Instances
          1.        75
          2.        76
        2.       MCU Domain Instances
          1.        78
      13. 5.3.12 GPMC
        1.       MAIN Domain Instances
          1.        81
          2. 5.3.12.1.1 GPMC0 IOSETs (ALV)
      14. 5.3.13 I2C
        1.       MAIN Domain Instances
          1.        85
          2.        86
          3.        87
          4.        88
        2.       MCU Domain Instances
          1.        90
          2.        91
      15. 5.3.14 MCAN
        1.       MAIN Domain Instances
          1.        94
          2.        95
      16. 5.3.15 SPI (MCSPI)
        1.       MAIN Domain Instances
          1.        98
          2.        99
          3.        100
          4.        101
          5.        102
        2.       MCU Domain Instances
          1.        104
          2.        105
      17. 5.3.16 MMC
        1.       MAIN Domain Instances
          1.        108
          2.        109
      18. 5.3.17 OSPI
        1.       MAIN Domain Instances
          1.        112
      19. 5.3.18 Power Supply
        1.       114
      20. 5.3.19 PRU_ICSSG
        1.       MAIN Domain Instances
          1.        117
          2.        118
      21. 5.3.20 Reserved
        1.       120
      22. 5.3.21 SERDES
        1.       MAIN Domain Instances
          1.        123
      23. 5.3.22 System and Miscellaneous
        1. 5.3.22.1 Boot Mode Configuration
          1.        MAIN Domain Instances
            1.         127
        2. 5.3.22.2 Clocking
          1.        MCU Domain Instances
            1.         130
        3. 5.3.22.3 SYSTEM
          1.        MAIN Domain Instances
            1.         133
          2.        MCU Domain Instances
            1.         135
        4. 5.3.22.4 VMON
          1.        137
      24. 5.3.23 TIMER
        1.       MAIN Domain Instances
          1.        140
        2.       MCU Domain Instances
          1.        142
      25. 5.3.24 UART
        1.       MAIN Domain Instances
          1.        145
          2.        146
          3.        147
          4.        148
          5.        149
          6.        150
          7.        151
        2.       MCU Domain Instances
          1.        153
          2.        154
      26. 5.3.25 USB
        1.       MAIN Domain Instances
          1.        157
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Power Consumption Summary
    7. 6.7  Electrical Characteristics
      1. 6.7.1  I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.7.2  Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.7.3  High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 6.7.4  eMMCPHY Electrical Characteristics
      5. 6.7.5  SDIO Electrical Characteristics
      6. 6.7.6  LVCMOS Electrical Characteristics
      7. 6.7.7  ADC12B Electrical Characteristics (ALV package)
      8. 6.7.8  ADC10B Electrical Characteristics (ALX package)
      9. 6.7.9  USB2PHY Electrical Characteristics
      10. 6.7.10 SerDes PHY Electrical Characteristics
      11. 6.7.11 DDR Electrical Characteristics
    8. 6.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.8.2 Hardware Requirements
      3. 6.8.3 Programming Sequence
      4. 6.8.4 Impact to Your Hardware Warranty
    9. 6.9  Thermal Resistance Characteristics
      1. 6.9.1 Thermal Resistance Characteristics
    10. 6.10 Timing and Switching Characteristics
      1. 6.10.1 Timing Parameters and Information
      2. 6.10.2 Power Supply Requirements
        1. 6.10.2.1 Power Supply Slew Rate Requirement
        2. 6.10.2.2 Power Supply Sequencing
          1. 6.10.2.2.1 Power-Up Sequencing
          2. 6.10.2.2.2 Power-Down Sequencing
      3. 6.10.3 System Timing
        1. 6.10.3.1 Reset Timing
        2. 6.10.3.2 Safety Signal Timing
        3. 6.10.3.3 Clock Timing
      4. 6.10.4 Clock Specifications
        1. 6.10.4.1 Input Clocks / Oscillators
          1. 6.10.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 6.10.4.1.1.1 Load Capacitance
            2. 6.10.4.1.1.2 Shunt Capacitance
          2. 6.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
        2. 6.10.4.2 Output Clocks
        3. 6.10.4.3 PLLs
        4. 6.10.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.10.5 Peripherals
        1. 6.10.5.1  CPSW3G
          1. 6.10.5.1.1 CPSW3G MDIO Timing
          2. 6.10.5.1.2 CPSW3G RMII Timing
          3. 6.10.5.1.3 CPSW3G RGMII Timing
          4. 6.10.5.1.4 CPSW3G IOSETs
        2. 6.10.5.2  DDRSS
        3. 6.10.5.3  ECAP
        4. 6.10.5.4  EPWM
        5. 6.10.5.5  EQEP
        6. 6.10.5.6  FSI
        7. 6.10.5.7  GPIO
        8. 6.10.5.8  GPMC
          1. 6.10.5.8.1 GPMC and NOR Flash — Synchronous Mode
          2. 6.10.5.8.2 GPMC and NOR Flash — Asynchronous Mode
          3. 6.10.5.8.3 GPMC and NAND Flash — Asynchronous Mode
          4. 6.10.5.8.4 GPMC0 IOSETs (ALV)
        9. 6.10.5.9  I2C
        10. 6.10.5.10 MCAN
        11. 6.10.5.11 MCSPI
          1. 6.10.5.11.1 MCSPI — Controller Mode
          2. 6.10.5.11.2 MCSPI — Peripheral Mode
        12. 6.10.5.12 MMCSD
          1. 6.10.5.12.1 MMC0 - eMMC Interface
            1. 6.10.5.12.1.1 Legacy SDR Mode
            2. 6.10.5.12.1.2 High Speed SDR Mode
            3. 6.10.5.12.1.3 High Speed DDR Mode
            4. 6.10.5.12.1.4 HS200 Mode
          2. 6.10.5.12.2 MMC1 - SD/SDIO Interface
            1. 6.10.5.12.2.1 Default Speed Mode
            2. 6.10.5.12.2.2 High Speed Mode
            3. 6.10.5.12.2.3 UHS–I SDR12 Mode
            4. 6.10.5.12.2.4 UHS–I SDR25 Mode
            5. 6.10.5.12.2.5 UHS–I SDR50 Mode
            6. 6.10.5.12.2.6 UHS–I DDR50 Mode
            7. 6.10.5.12.2.7 UHS–I SDR104 Mode
        13. 6.10.5.13 CPTS
        14. 6.10.5.14 OSPI
          1. 6.10.5.14.1 OSPI0 PHY Mode
            1. 6.10.5.14.1.1 OSPI0 With PHY Data Training
            2. 6.10.5.14.1.2 OSPI0 Without Data Training
              1. 6.10.5.14.1.2.1 OSPI0 PHY SDR Timing
              2. 6.10.5.14.1.2.2 OSPI0 PHY DDR Timing
          2. 6.10.5.14.2 OSPI0 Tap Mode
            1. 6.10.5.14.2.1 OSPI0 Tap SDR Timing
            2. 6.10.5.14.2.2 OSPI0 Tap DDR Timing
        15. 6.10.5.15 PCIe
        16. 6.10.5.16 PRU_ICSSG
          1. 6.10.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)
            1. 6.10.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing
            2. 6.10.5.16.1.2 PRU_ICSSG PRU Parallel Capture Mode Timing
            3. 6.10.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing
            4. 6.10.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface
              1. 6.10.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing
          2. 6.10.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 6.10.5.16.2.1 PRU_ICSSG PWM Timing
          3. 6.10.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)
            1. 6.10.5.16.3.1 PRU_ICSSG IEP Timing
          4. 6.10.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)
            1. 6.10.5.16.4.1 PRU_ICSSG UART Timing
          5. 6.10.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)
            1. 6.10.5.16.5.1 PRU_ICSSG ECAP Timing
          6. 6.10.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 6.10.5.16.6.1 PRU_ICSSG MDIO Timing
            2. 6.10.5.16.6.2 PRU_ICSSG MII Timing
            3. 6.10.5.16.6.3 PRU_ICSSG RGMII Timing
        17. 6.10.5.17 Timers
        18. 6.10.5.18 UART
        19. 6.10.5.19 USB
      6. 6.10.6 Emulation and Debug
        1. 6.10.6.1 Trace
        2. 6.10.6.2 JTAG
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-R5F Subsystem (R5FSS)
      2. 7.2.2 Arm Cortex-M4F (M4FSS)
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)
    4. 7.4 Other Subsystems
      1. 7.4.1 PDMA Controller
      2. 7.4.2 Peripherals
        1. 7.4.2.1  ADC
        2. 7.4.2.2  DCC
        3. 7.4.2.3  Dual Date Rate (DDR) External Memory Interface (DDRSS)
        4. 7.4.2.4  ECAP
        5. 7.4.2.5  EPWM
        6. 7.4.2.6  ELM
        7. 7.4.2.7  ESM
        8. 7.4.2.8  GPIO
        9. 7.4.2.9  EQEP
        10. 7.4.2.10 General-Purpose Memory Controller (GPMC)
        11. 7.4.2.11 I2C
        12. 7.4.2.12 MCAN
        13. 7.4.2.13 MCRC Controller
        14. 7.4.2.14 MCSPI
        15. 7.4.2.15 MMCSD
        16. 7.4.2.16 OSPI
        17. 7.4.2.17 Peripheral Component Interconnect Express (PCIe)
        18. 7.4.2.18 Serializer/Deserializer (SerDes) PHY
        19. 7.4.2.19 Real Time Interrupt (RTI/WWDT)
        20. 7.4.2.20 Dual Mode Timer (DMTIMER)
        21. 7.4.2.21 UART
        22. 7.4.2.22 Universal Serial Bus Subsystem (USBSS)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
        1. 8.1.1.1 Power Supply Designs
        2. 8.1.1.2 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 General Routing Guidelines
      2. 8.2.2 DDR Board Design and Layout Guidelines
      3. 8.2.3 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.3.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.3.2 External Board Loopback
        3. 8.2.3.3 DQS (only available in Octal SPI devices)
      4. 8.2.4 USB VBUS Design Guidelines
      5. 8.2.5 System Power Supply Monitor Design Guidelines
      6. 8.2.6 High Speed Differential Signal Routing Guidance
      7. 8.2.7 Thermal Solution Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
      2. 8.3.2 Oscillator Ground Connection
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
      1. 9.3.1 Information About Cautions and Warnings
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALV|441
  • ALX|293
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.2.1 AM243x Package Comparison Table (ALV vs. ALX)

Table 5-2 AM243x Package Comparison Table (ALV vs. ALX)
AM243x_ALV
BALL #		 AM243x_ALV
SIGNAL NAME		 AM243x_ALX
BALL #		 AM243x_ALX
SIGNAL NAME
A1 VSS A1 VSS
A2 DDR0_DQ1 A2 VSS
A3 DDR0_DQ0 A3 TDI
A4 DDR0_DQ3
A5 VSS A5 MCU_RESETZ
A6 VSS A6 MCU_RESETSTATZ
A7 MCU_SPI1_CS0
A8 MCU_UART0_TXD A8 SPI0_D0
A9 MCU_UART0_RXD A9 UART0_RTSN
A10 MCU_I2C0_SDA
A11 MCU_I2C1_SCL A11 UART1_RTSN
A12 TDO A12 UART1_TXD
A13 SPI0_D0
A14 SPI0_D1 A14 MCAN0_RX
A15 SPI1_D1 A15 MCAN1_RX
A16 UART0_RTSN
A17 MCAN0_TX A17 I2C1_SCL
A18 I2C0_SCL A18 EXT_REFCLK1
A19 EXT_REFCLK1
A20 MCU_SAFETY_ERRORN A20 VSS
A21 VSS A21 VSS
B1 DDR0_DQS0_N B1 VSS
B2 DDR0_DM0 B2 MCU_UART0_TXD
B3 DDR0_DQ4 B3 EMU1
B4 DDR0_DQ7 B4 TMS
B5 DDR0_DQ2 B5 TDO
B6 MCU_SPI0_D1 B6 TRSTN
B7 MCU_SPI1_CS1 B7 SPI0_CS1
B8 MCU_UART1_CTSN B8 SPI0_CLK
B9 MCU_UART1_RTSN B9 UART0_CTSN
B10 MCU_I2C1_SDA B10 UART0_RXD
B11 TCK B11 UART0_TXD
B12 MCU_RESETZ B12 UART1_RXD
B13 MCU_RESETSTATZ B13 MCAN0_TX
B14 SPI1_CS0 B14 MCAN1_TX
B15 SPI1_D0 B15 I2C0_SDA
B16 UART0_CTSN B16 I2C0_SCL
B17 MCAN0_RX B17 MMC1_SDCD
B18 I2C0_SDA B18 I2C1_SDA
B19 I2C1_SDA B19 USB0_DRVVBUS
B20 MCU_OSC0_XO B20 MCU_SAFETY_ERRORN
B21 MCU_PORZ B21 VSS
C1 DDR0_DQS0
C2 DDR0_DQ6 C2 MCU_UART0_RTSN
C3 VSS
C4 DDR0_DQ5
C5 DDR0_A1 C5 EMU0
C6 MCU_SPI0_CS1 C6 TCK
C7 MCU_SPI1_D0
C8 MCU_SPI1_D1
C9 MCU_UART1_RXD C9 SPI0_D1
C10 VSS
C11 TDI C11 UART1_CTSN
C12 TMS
C13 SPI0_CS1 C13 VDDSHV0
C14 SPI1_CLK
C15 VSS
C16 UART0_TXD C16 MMC1_SDWP
C17 MCAN1_TX C17 RESET_REQZ
C18 I2C1_SCL
C19 EXTINTN
C20 MMC1_SDWP C20 MCU_PORZ
C21 MCU_OSC0_XI C21 MCU_OSC0_XO
D1 VSS D1 PRG0_PRU1_GPO18
D2 DDR0_A0 D2 PRG0_MDIO0_MDC
D3 DDR0_A4
D4 DDR0_A3 D4 MCU_UART0_CTSN
D5 DDR0_RESET0_N
D6 MCU_SPI0_CS0 D6 MCU_UART0_RXD
D7 MCU_SPI1_CLK
D8 MCU_UART0_CTSN
D9 MCU_UART1_TXD D9 CAP_VDDS_MCU
D10 EMU0 D10 VSS
D11 TRSTN
D12 SPI0_CS0 D12 CAP_VDDS0
D13 SPI0_CLK D13 VDDSHV0
D14 SPI1_CS1
D15 UART0_RXD
D16 UART1_CTSN D16 VSS
D17 MCAN1_RX D17 VSS
D18 ECAP0_IN_APWM_OUT D18 PORZ_OUT
D19 MMC1_SDCD
D20 ADC0_AIN3 D20 MCU_OSC0_XI
D21 RSVD
E1 DDR0_CK0_N E1 PRG0_PRU0_GPO17
E2 DDR0_A2 E2 PRG0_PRU0_GPO7
E3 DDR0_CS0_N E3 PRG0_PRU1_GPO5
E4 DDR0_CS1_N E4 PRG0_MDIO0_MDIO
E5 DDR0_ODT0
E6 MCU_SPI0_CLK E6 VSS
E7 MCU_SPI0_D0 E7 VDDSHV_MCU
E8 MCU_UART0_RTSN E8 VDDSHV_MCU
E9 MCU_I2C0_SCL E9 VDDSHV_MCU
E10 EMU1
E11 VSS E11 VSS
E12 VMON_1P8_SOC
E13 VSS E13 VSS
E14 UART1_TXD E14 VDDSHV0
E15 UART1_RXD E15 VMON_3P3_SOC
E16 UART1_RTSN E16 VPP
E17 PORZ_OUT
E18 RESET_REQZ
E19 USB0_DRVVBUS E19 RESETSTATZ
E20 ADC0_AIN7 E20 ADC0_AIN7
E21 ADC0_AIN2 E21 ADC0_AIN5
F1 DDR0_CK0
F2 DDR0_A5 F2 PRG0_PRU0_GPO5
F3 DDR0_CKE1 F3 PRG0_PRU1_GPO19
F4 DDR0_CKE0 F4 PRG0_PRU1_GPO8
F5 DDR0_ODT1 F5 PRG0_PRU1_GPO6
F6 DDR0_RAS_N
F7 VDDS_DDR
F8 VSS F8 VSS
F9 VDDSHV_MCU
F10 VSS
F11 VDDSHV0 F11 VDD_CORE
F12 RSVD
F13 VMON_3P3_MCU
F14 VMON_3P3_SOC F14 VMON_1P8_SOC
F15 VSS
F16 RESETSTATZ
F17 RSVD F17 VSS
F18 MMC0_CALPAD F18 VDDS_OSC
F19 ADC0_AIN6 F19 ADC0_AIN1
F20 ADC0_AIN1 F20 ADC0_AIN3
F21 ADC0_AIN5 F21 ADC0_AIN2
G1 VSS G1 PRG0_PRU0_GPO2
G2 DDR0_BG0 G2 PRG0_PRU0_GPO19
G3 VSS
G4 DDR0_BA0
G5 DDR0_BA1 G5 VDDR_CORE
G6 VDDS_DDR G6 VDDR_CORE
G7 VSS
G8 VDDSHV_MCU
G9 VSS G9 VDDA_PLL1
G10 VDDSHV_MCU G10 VDD_CORE
G11 VDDA_TEMP0 G11 VDDA_TEMP0
G12 VDDSHV0 G12 VDDA_PLL2
G13 RSVD G13 VMON_VSYS
G14 VDDSHV0
G15 VPP
G16 VSS G16 VSS
G17 MMC0_DAT7 G17 VDDA_ADC
G18 MMC0_CLK
G19 MMC0_DS
G20 ADC0_AIN0 G20 ADC0_AIN6
G21 ADC0_AIN4
H1 DDR0_ALERT_N H1 PRG0_PRU0_GPO3
H2 DDR0_ACT_N H2 PRG0_PRU0_GPO6
H3 DDR0_BG1
H4 DDR0_WE_N
H5 DDR0_CAL0 H5 PRG0_PRU0_GPO8
H6 VSS H6 VSS
H7 VDDS_DDR H7 VSS
H8 VSS H8 VDD_CORE
H9 VDDA_PLL1
H10 CAP_VDDS_MCU
H11 VSS H11 RSVD
H12 CAP_VDDS0
H13 VDDS_OSC
H14 VDD_DLL_MMC0 H14 VDDA_MCU
H15 VDDA_3P3_SDIO H15 VDD_CORE
H16 RSVD H16 VSS
H17 MMC0_DAT4 H17 VDDA_ADC
H18 MMC0_DAT6
H19 MMC0_DAT5
H20 VSS H20 ADC0_AIN4
H21 VSS H21 ADC0_AIN0
J1 DDR0_A11
J2 DDR0_A6 J2 PRG0_PRU1_GPO1
J3 DDR0_A8 J3 PRG0_PRU0_GPO0
J4 DDR0_A9 J4 PRG0_PRU0_GPO1
J5 DDR0_CAS_N J5 VSS
J6 VDDS_DDR J6 VSS
J7 VSS
J8 VDDS_DDR_C
J9 VSS J9 VDD_CORE
J10 VDD_CORE J10 VDDR_CORE
J11 VDDA_PLL2 J11 VSS
J12 VDD_CORE J12 VDDR_CORE
J13 VDDA_ADC J13 RSVD
J14 VSS
J15 ADC_REFP
J16 ADC_REFN J16 VSS
J17 MMC0_DAT3 J17 CAP_VDDSHV_MMC1
J18 MMC0_DAT2 J18 MMC1_DAT0
J19 MMC1_CMD J19 MMC1_DAT1
J20 MMC0_DAT1 J20 MMC1_CLK
J21 MMC0_CMD J21 MMC1_CMD
K1 RSVD K1 PRG0_PRU0_GPO12
K2 RSVD K2 PRG0_PRU0_GPO4
K3 DDR0_A10
K4 DDR0_A13 K4 PRG0_PRU0_GPO18
K5 DDR0_PAR
K6 VSS K6 VSS
K7 VDDS_DDR K7 VSS
K8 VSS K8 VSS
K9 VDD_CORE
K10 VMON_VSYS
K11 VDD_CORE K11 VDD_CORE
K12 VDDA_MCU
K13 VDD_MMC0
K14 VDDS_MMC0 K14 VDD_CORE
K15 CAP_VDDSHV_MMC1 K15 VDDA_3P3_SDIO
K16 VMON_1P8_MCU K16 VSS
K17 OSPI0_CSN2
K18 MMC1_DAT3 K18 MMC1_DAT3
K19 MMC1_DAT2
K20 MMC0_DAT0 K20 MMC1_DAT2
K21 MMC1_DAT0
L1 VSS L1 PRG0_PRU0_GPO11
L2 DDR0_DQ10 L2 PRG0_PRU1_GPO3
L3 VSS L3 PRG0_PRU1_GPO4
L4 DDR0_DQ9
L5 DDR0_A7 L5 PRG0_PRU1_GPO0
L6 VDDS_DDR L6 VDDSHV1
L7 VSS
L8 VDD_CORE
L9 VSS L9 VDD_CORE
L10 VDDR_CORE L10 VSS
L11 VDDA_TEMP1 L11 VSS
L12 VDD_CORE L12 VSS
L13 CAP_VDDS5 L13 VDD_CORE
L14 VDDSHV5
L15 VDDSHV5
L16 VSS L16 VDDSHV5
L17 OSPI0_CSN3 L17 VDDSHV5
L18 OSPI0_CSN1
L19 OSPI0_CSN0 L19 OSPI0_D0
L20 MMC1_CLK L20 OSPI0_CSN0
L21 MMC1_DAT1 L21 OSPI0_D2
M1 DDR0_DQS1_N
M2 DDR0_DM1 M2 PRG0_PRU1_GPO2
M3 DDR0_DQ11
M4 DDR0_DQ14 M4 PRG0_PRU1_GPO15
M5 DDR0_A12
M6 VSS M6 VDDSHV1
M7 VDDSHV1 M7 VSS
M8 VSS M8 VDD_CORE
M9 VDD_CORE
M10 VSS
M11 VDD_CORE M11 VDDA_TEMP1
M12 VSS
M13 VDDR_CORE
M14 VDDSHV4 M14 VDD_CORE
M15 VDDSHV4 M15 VSS
M16 CAP_VDDS4 M16 VSS
M17 OSPI0_D7
M18 OSPI0_D1 M18 CAP_VDDS5
M19 OSPI0_D0
M20 OSPI0_D2 M20 OSPI0_CSN1
M21 OSPI0_D3 M21 OSPI0_LBCLKO
N1 DDR0_DQS1 N1 PRG0_PRU0_GPO13
N2 DDR0_DQ15 N2 PRG0_PRU0_GPO14
N3 DDR0_DQ13 N3 PRG0_PRU0_GPO16
N4 DDR0_DQ12 N4 PRG0_PRU0_GPO15
N5 DDR0_DQ8 N5 CAP_VDDS1
N6 VDDSHV1 N6 VSS
N7 VSS
N8 VDD_CORE
N9 VSS N9 VDD_CORE
N10 VDD_CORE N10 VDD_CORE
N11 VSS N11 VSS
N12 VDDA_PLL0 N12 VDDA_PLL0
N13 VSS N13 VSS
N14 CAP_VDDS3
N15 VSS
N16 GPMC0_WPN N16 VDDSHV4
N17 GPMC0_DIR N17 VDDSHV4
N18 OSPI0_D6 N18 CAP_VDDS4
N19 OSPI0_DQS N19 OSPI0_D3
N20 OSPI0_CLK N20 OSPI0_D1
N21 OSPI0_LBCLKO
P1 VSS P1 PRG0_PRU1_GPO11
P2 PRG0_MDIO0_MDIO P2 PRG0_PRU1_GPO12
P3 PRG0_MDIO0_MDC
P4 PRG0_PRU1_GPO5
P5 PRG0_PRU1_GPO18 P5 VDDSHV1
P6 VSS P6 VDDSHV1
P7 VDDSHV1 P7 VSS
P8 VSS P8 VDDR_CORE
P9 VDD_CORE
P10 VSS
P11 VDDA_0P85_SERDES0_C P11 VSS
P12 VDDA_0P85_SERDES0
P13 VDDA_0P85_SERDES0
P14 VDDSHV3 P14 VDDR_CORE
P15 VDDSHV3 P15 VSS
P16 GPMC0_ADVN_ALE P16 VSS
P17 GPMC0_BE0N_CLE P17 OSPI0_DQS
P18 VSS
P19 GPMC0_CSN2
P20 OSPI0_D5 P20 OSPI0_CLK
P21 OSPI0_D4 P21 GPMC0_BE1N
R1 PRG0_PRU1_GPO8
R2 PRG0_PRU1_GPO19 R2 PRG0_PRU1_GPO9
R3 PRG0_PRU0_GPO5
R4 PRG0_PRU0_GPO1
R5 PRG0_PRU1_GPO6 R5 PRG0_PRU1_GPO14
R6 PRG0_PRU0_GPO13 R6 VSS
R7 VSS
R8 VDDSHV2
R9 VSS R9 VDD_CORE
R10 VDDSHV2 R10 VDDR_CORE
R11 CAP_VDDS2 R11 VSS
R12 VSS R12 VDD_CORE
R13 VDDA_3P3_USB0 R13 VDD_CORE
R14 VDDA_1P8_SERDES0
R15 VDDA_1P8_USB0
R16 GPMC0_AD10 R16 CAP_VDDS3
R17 GPMC0_CLK R17 VDDSHV3
R18 GPMC0_OEN_REN
R19 GPMC0_CSN0
R20 GPMC0_CSN1 R20 GPMC0_AD1
R21 GPMC0_CSN3 R21 GPMC0_AD0
T1 PRG0_PRU0_GPO7 T1 PRG0_PRU1_GPO17
T2 PRG0_PRU0_GPO8 T2 PRG1_PRU0_GPO17
T3 PRG0_PRU0_GPO6 T3 PRG0_PRU1_GPO16
T4 PRG0_PRU1_GPO3 T4 PRG0_PRU1_GPO13
T5 PRG0_PRU0_GPO15 T5 PRG0_PRU1_GPO7
T6 PRG0_PRU1_GPO13
T7 CAP_VDDS1
T8 VSS T8 VDDSHV2
T9 VDDSHV2
T10 VSS
T11 VSS T11 VDDSHV2
T12 VDDA_0P85_USB0
T13 SERDES0_REXT
T14 USB0_VBUS T14 VSS
T15 VSS
T16 VSS
T17 GPMC0_AD9 T17 VDDSHV3
T18 GPMC0_AD2 T18 GPMC0_AD6
T19 GPMC0_BE1N T19 GPMC0_AD2
T20 GPMC0_AD0 T20 GPMC0_AD5
T21 GPMC0_WEN
U1 PRG0_PRU0_GPO17 U1 PRG0_PRU0_GPO10
U2 PRG0_PRU0_GPO2 U2 PRG0_PRU1_GPO10
U3 VSS U3 PRG1_PRU0_GPO19
U4 PRG0_PRU0_GPO16
U5 PRG0_PRU1_GPO15
U6 PRG0_PRU1_GPO14 U6 VSS
U7 PRG1_PRU0_GPO17 U7 VDDSHV2
U8 PRG1_PRU0_GPO1 U8 VDDSHV2
U9 PRG1_PRU0_GPO12 U9 CAP_VDDS2
U10 PRG1_PRU1_GPO13
U11 PRG1_PRU1_GPO6 U11 VDDSHV2
U12 PRG1_PRU1_GPO8
U13 PRG1_PRU0_GPO7 U13 PRG1_PRU1_GPO10
U14 PRG1_PRU0_GPO10 U14 PRG1_PRU0_GPO5
U15 PRG1_PRU0_GPO9 U15 VDDA_1P8_USB0
U16 USB0_ID U16 VDDA_3P3_USB0
U17 USB0_RCALIB
U18 GPMC0_AD4 U18 GPMC0_AD8
U19 GPMC0_AD5 U19 GPMC0_AD7
U20 GPMC0_AD3 U20 GPMC0_AD9
U21 GPMC0_AD1 U21 GPMC0_AD4
V1 PRG0_PRU0_GPO18
V2 PRG0_PRU0_GPO3 V2 PRG1_MDIO0_MDIO
V3 PRG0_PRU1_GPO2
V4 PRG0_PRU0_GPO14 V4 PRG1_PRU0_GPO0
V5 PRG0_PRU1_GPO17 V5 PRG1_PRU0_GPO11
V6 PRG0_PRU1_GPO10 V6 PRG1_PRU0_GPO13
V7 PRG1_PRU0_GPO18
V8 PRG1_PRU0_GPO3
V9 PRG1_PRU0_GPO16 V9 PRG1_PRU1_GPO15
V10 PRG1_PRU1_GPO12 V10 PRG1_PRU1_GPO6
V11 PRG1_PRU1_GPO1
V12 PRG1_PRU1_GPO19 V12 PRG1_PRU1_GPO3
V13 PRG1_PRU0_GPO5 V13 PRG1_PRU0_GPO7
V14 PRG1_PRU1_GPO9
V15 PRG1_PRU1_GPO7
V16 RSVD V16 VDDA_0P85_USB0
V17 VSS
V18 GPMC0_AD13 V18 USB0_VBUS
V19 GPMC0_AD8
V20 GPMC0_AD6 V20 GPMC0_AD10
V21 GPMC0_AD7 V21 GPMC0_AD3
W1 PRG0_PRU0_GPO19 W1 PRG1_MDIO0_MDC
W2 PRG0_PRU1_GPO1 W2 PRG1_PRU0_GPO12
W3 PRG0_PRU1_GPO4
W4 PRG0_PRU1_GPO11
W5 PRG0_PRU1_GPO7 W5 PRG1_PRU0_GPO1
W6 PRG0_PRU0_GPO9 W6 PRG1_PRU0_GPO16
W7 PRG1_PRU0_GPO19
W8 PRG1_PRU0_GPO2
W9 PRG1_PRU0_GPO13 W9 PRG1_PRU1_GPO14
W10 VSS
W11 PRG1_PRU1_GPO0 W11 PRG1_PRU1_GPO8
W12 PRG1_PRU1_GPO4
W13 PRG1_PRU0_GPO8 W13 PRG1_PRU0_GPO10
W14 PRG1_PRU1_GPO10
W15 RSVD
W16 SERDES0_REFCLK0N W16 PRG1_PRU0_GPO9
W17 SERDES0_REFCLK0P W17 USB0_RCALIB
W18 VSS
W19 GPMC0_WAIT0
W20 GPMC0_AD11 W20 GPMC0_AD11
W21 GPMC0_AD12
Y1 PRG0_PRU0_GPO0 Y1 VSS
Y2 PRG0_PRU1_GPO0 Y2 PRG1_PRU0_GPO6
Y3 PRG0_PRU0_GPO11 Y3 PRG0_PRU0_GPO9
Y4 PRG0_PRU1_GPO12 Y4 PRG1_PRU0_GPO18
Y5 PRG0_PRU1_GPO9 Y5 PRG1_PRU0_GPO3
Y6 PRG1_MDIO0_MDC Y6 PRG1_PRU1_GPO11
Y7 PRG1_PRU0_GPO0 Y7 PRG1_PRU0_GPO15
Y8 PRG1_PRU0_GPO4 Y8 PRG1_PRU1_GPO16
Y9 PRG1_PRU0_GPO15 Y9 PRG1_PRU1_GPO13
Y10 PRG1_PRU1_GPO16 Y10 PRG1_PRU1_GPO1
Y11 PRG1_PRU1_GPO15 Y11 PRG1_PRU1_GPO2
Y12 PRG1_PRU1_GPO3 Y12 PRG1_PRU1_GPO4
Y13 PRG1_PRU1_GPO18 Y13 PRG1_PRU0_GPO8
Y14 VSS Y14 PRG1_PRU1_GPO7
Y15 SERDES0_RX0_N Y15 PRG1_PRU1_GPO18
Y16 SERDES0_RX0_P Y16 PRG1_PRU1_GPO9
Y17 VSS Y17 USB0_ID
Y18 GPMC0_WAIT1 Y18 GPMC0_AD14
Y19 VSS Y19 GPMC0_AD13
Y20 GPMC0_AD15 Y20 GPMC0_AD12
Y21 GPMC0_AD14 Y21 VSS
AA1 VSS AA1 VSS
AA2 PRG0_PRU0_GPO4 AA2 VSS
AA3 PRG0_PRU0_GPO12
AA4 PRG0_PRU1_GPO16 AA4 PRG1_PRU0_GPO2
AA5 PRG0_PRU0_GPO10 AA5 PRG1_PRU0_GPO4
AA6 PRG1_MDIO0_MDIO
AA7 PRG1_PRU0_GPO6 AA7 PRG1_PRU0_GPO14
AA8 PRG1_PRU0_GPO11 AA8 PRG1_PRU1_GPO12
AA9 PRG1_PRU0_GPO14
AA10 PRG1_PRU1_GPO11 AA10 PRG1_PRU1_GPO0
AA11 PRG1_PRU1_GPO14 AA11 PRG1_PRU1_GPO5
AA12 PRG1_PRU1_GPO2
AA13 PRG1_PRU1_GPO5 AA13 PRG1_PRU1_GPO19
AA14 PRG1_PRU1_GPO17 AA14 PRG1_PRU1_GPO17
AA15 VSS
AA16 SERDES0_TX0_N AA16 USB0_DP
AA17 SERDES0_TX0_P AA17 USB0_DM
AA18 VSS
AA19 USB0_DP AA19 GPMC0_AD15
AA20 USB0_DM AA20 VSS
AA21 VSS AA21 VSS