SLUSFQ1A December   2024  – December 2024 BQ41Z90

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions:
  6. 5 Pin Equivalent Diagrams
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Supply Current
    6. 6.6  Power Selector
    7. 6.7  Current Wake Detector
    8. 6.8  General Purpose Input-Outputs
    9. 6.9  Aux REGOUT LDO
    10. 6.10 LD Pin
    11. 6.11 Shelf Timer
    12. 6.12 Cell Balancing
    13. 6.13 Comparator-Based Detections (SCOMP)
    14. 6.14 SCOMP Timing Requirements
    15. 6.15 SCD Comparator
    16. 6.16 High-side NFET Drivers (CHG and DSG and PCHG and PDSG)
    17. 6.17 FUSE Pin
    18. 6.18 Flash Memory
    19. 6.19 Interface I/O
    20. 6.20 I2C Interface Timing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Functional Modes
        1. 7.3.1.1 Analog Front End (AFE)
        2. 7.3.1.2 Power Management
          1. 7.3.1.2.1 Power Mode Block Configuration
          2. 7.3.1.2.2 Power Supply Control
            1. 7.3.1.2.2.1 HIBERNATE Mode
            2. 7.3.1.2.2.2 SHUTDOWN Mode
            3. 7.3.1.2.2.3 SHELF Mode
            4. 7.3.1.2.2.4 Wake Functionality
          3. 7.3.1.2.3 Power Management Unit
            1. 7.3.1.2.3.1 PMU Overview
          4. 7.3.1.2.4 Thermal Shutdown
          5. 7.3.1.2.5 Low Drop Out Regulators (LDOs)
            1. 7.3.1.2.5.1 REG18
            2. 7.3.1.2.5.2 REG135
            3. 7.3.1.2.5.3 REGIO
            4. 7.3.1.2.5.4 REGOUT
        3. 7.3.1.3 Reset Management
          1. 7.3.1.3.1 RST_SD Pin Operation
          2. 7.3.1.3.2 AFE Watchdog
        4. 7.3.1.4 Diagnostics Features
        5. 7.3.1.5 Internal Oscillators
          1. 7.3.1.5.1 Low Frequency Oscillator (LFO)
          2. 7.3.1.5.2 High Frequency Oscillator (HFO)
          3. 7.3.1.5.3 Low Power Oscillator (LPO)
      2. 7.3.2 Temperature Measurement
        1. 7.3.2.1 External Temperature Measurement Support
        2. 7.3.2.2 Internal Temperature Sensor
      3. 7.3.3 Random Cell Connection Support
        1. 7.3.3.1 Usage of VC Pins for Cells Versus Interconnect
        2. 7.3.3.2 Unused Pins
      4. 7.3.4 Cell Balancing Support
        1. 7.3.4.1 Open Wire Detection
      5. 7.3.5 Protection and Charge Control Outputs
        1. 7.3.5.1 High-Side NFET Drivers
        2. 7.3.5.2 PRECHARGE and PREDISCHARGE Modes
        3. 7.3.5.3 FET Configuration
        4. 7.3.5.4 CFETOFF, DFETOFF Pin Functionality
        5. 7.3.5.5 DDSG and DCHG Pin Operation
        6. 7.3.5.6 Hardware Fault Detection (SCOMP and SCD)
        7. 7.3.5.7 FET UVLO Protection
        8. 7.3.5.8 Fuse Drive
      6. 7.3.6 Load Detect Functionality
      7. 7.3.7 MCU Peripherals
        1. 7.3.7.1 General Purpose and Special Function I/O
          1. 7.3.7.1.1 Low Voltage RAx I/O
          2. 7.3.7.1.2 Low Voltage RCx I/O
          3. 7.3.7.1.3 Constant Current Sink I/O
        2. 7.3.7.2 Communication Interfaces
          1. 7.3.7.2.1 I2C Interface
          2. 7.3.7.2.2 SMBus Interface
        3. 7.3.7.3 Authentication Support
          1. 7.3.7.3.1 ECC Authentication
          2. 7.3.7.3.2 SHA-1 Support
          3. 7.3.7.3.3 SHA-2 Support
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PVP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3 Recommended Operating Conditions

Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 105°C and VBAT = 5 V to 80 V (unless otherwise noted)(1)
PARAMETERTEST CONDITIONSMINNOMMAXUNIT
VDDSupply voltageBAT pin, IREG18 ≤ 22mAVSWITCHOVER–80V
VCC pin580V
VINInput voltage rangePACK, LD080V
RAx (SDL0, SCLK0, SDL1, SCLK1)05.5V
RCx 0VREGIOV
RADCx, TSx, LEDx, DFETOFF, CFETOFF, RST_SD0VREG18 + 0.3V
SRP, SRN pins–0.250.5V
VC16VC15–0.2VC15+5V
VC15VC14–0.2VC14+5V
VC14VC13–0.2VC13+5V
VC13VC12–0.2VC12+5V
VC12VC11–0.2VC11+5V
VC11VC10–.02VC10+5V
VC10VC9–.02VC9+5V
VC9VC8–0.2VC8+5V
VC8VC7–0.2VC7+5V
VC7VC6–0.2VC6+5V
VC6VC5–0.2VC5 +5V
VC5VC4–0.2VC4+5V
VC4VC3–0.2VC3+5V
VC3VC2–0.2VC2+5V
VC2VC1–0.2VC1+5V
VC1VC0–.02VC0+5V
VC0–0.20.5V
VOUTOutput voltage rangeCHG, DSG, PCHG, PDSG080V
VOUTOutput voltage rangeFUSE028V
CBAT (1)BAT external capacitorDerated to 2.2V, 100V capacitor0.471µF
CVCC(1)VCC external capacitorDerated to 2.2V, 100V capacitor0.10.47µF
CREGIO (1)REGIO exteranl capacitorDerated to 3.3 V, 10V capacitor0.4712.2µF
CREG18 (1)REG18 external capacitorDerated to 1.8 V, 10V capacitor0.4712.2µF
CREG135 (1)REG135 external capacitorDerated to 1.35 V, 10V capacitor0.4712.2µF
CpCharge pump capacitorDerated to 2.2V, 100V capacitor1004702200nF
CC  External cell input capacitor Derated to 2.2V, 100V capacitor100nF
RC External cell measurement input  resistor20100Ω
RPACK (1)PACK series external resistorFor lowest Startup voltage21012kΩ
ISS(1)Maximum current through Vss pinIncludes LDOs, GPIO and Cell balancing200mA
TA(2)Operating free-air temperature–40105°C
(2) Additional cooling strategies may be necessary to keep junction temperature at recommended limits.