SLUSFQ1A December   2024  – December 2024 BQ41Z90

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions:
  6. 5 Pin Equivalent Diagrams
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Supply Current
    6. 6.6  Power Selector
    7. 6.7  Current Wake Detector
    8. 6.8  General Purpose Input-Outputs
    9. 6.9  Aux REGOUT LDO
    10. 6.10 LD Pin
    11. 6.11 Shelf Timer
    12. 6.12 Cell Balancing
    13. 6.13 Comparator-Based Detections (SCOMP)
    14. 6.14 SCOMP Timing Requirements
    15. 6.15 SCD Comparator
    16. 6.16 High-side NFET Drivers (CHG and DSG and PCHG and PDSG)
    17. 6.17 FUSE Pin
    18. 6.18 Flash Memory
    19. 6.19 Interface I/O
    20. 6.20 I2C Interface Timing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Functional Modes
        1. 7.3.1.1 Analog Front End (AFE)
        2. 7.3.1.2 Power Management
          1. 7.3.1.2.1 Power Mode Block Configuration
          2. 7.3.1.2.2 Power Supply Control
            1. 7.3.1.2.2.1 HIBERNATE Mode
            2. 7.3.1.2.2.2 SHUTDOWN Mode
            3. 7.3.1.2.2.3 SHELF Mode
            4. 7.3.1.2.2.4 Wake Functionality
          3. 7.3.1.2.3 Power Management Unit
            1. 7.3.1.2.3.1 PMU Overview
          4. 7.3.1.2.4 Thermal Shutdown
          5. 7.3.1.2.5 Low Drop Out Regulators (LDOs)
            1. 7.3.1.2.5.1 REG18
            2. 7.3.1.2.5.2 REG135
            3. 7.3.1.2.5.3 REGIO
            4. 7.3.1.2.5.4 REGOUT
        3. 7.3.1.3 Reset Management
          1. 7.3.1.3.1 RST_SD Pin Operation
          2. 7.3.1.3.2 AFE Watchdog
        4. 7.3.1.4 Diagnostics Features
        5. 7.3.1.5 Internal Oscillators
          1. 7.3.1.5.1 Low Frequency Oscillator (LFO)
          2. 7.3.1.5.2 High Frequency Oscillator (HFO)
          3. 7.3.1.5.3 Low Power Oscillator (LPO)
      2. 7.3.2 Temperature Measurement
        1. 7.3.2.1 External Temperature Measurement Support
        2. 7.3.2.2 Internal Temperature Sensor
      3. 7.3.3 Random Cell Connection Support
        1. 7.3.3.1 Usage of VC Pins for Cells Versus Interconnect
        2. 7.3.3.2 Unused Pins
      4. 7.3.4 Cell Balancing Support
        1. 7.3.4.1 Open Wire Detection
      5. 7.3.5 Protection and Charge Control Outputs
        1. 7.3.5.1 High-Side NFET Drivers
        2. 7.3.5.2 PRECHARGE and PREDISCHARGE Modes
        3. 7.3.5.3 FET Configuration
        4. 7.3.5.4 CFETOFF, DFETOFF Pin Functionality
        5. 7.3.5.5 DDSG and DCHG Pin Operation
        6. 7.3.5.6 Hardware Fault Detection (SCOMP and SCD)
        7. 7.3.5.7 FET UVLO Protection
        8. 7.3.5.8 Fuse Drive
      6. 7.3.6 Load Detect Functionality
      7. 7.3.7 MCU Peripherals
        1. 7.3.7.1 General Purpose and Special Function I/O
          1. 7.3.7.1.1 Low Voltage RAx I/O
          2. 7.3.7.1.2 Low Voltage RCx I/O
          3. 7.3.7.1.3 Constant Current Sink I/O
        2. 7.3.7.2 Communication Interfaces
          1. 7.3.7.2.1 I2C Interface
          2. 7.3.7.2.2 SMBus Interface
        3. 7.3.7.3 Authentication Support
          1. 7.3.7.3.1 ECC Authentication
          2. 7.3.7.3.2 SHA-1 Support
          3. 7.3.7.3.3 SHA-2 Support
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PVP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.16 High-side NFET Drivers (CHG and DSG and PCHG and PDSG)

Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 105°C and VBAT = 5 V to 80 V (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
V(FETON)CHG pin voltage with respect to BAT, DSG pin voltage with respect to LD/PACK, 6 V ≤ VBAT ≤ 80 V, VLD  ≤ VDSG(1)(2)VBAT ≥ 6V, CHG/DSG CL = 20nF, RGS = 10MΩ, charge pump normal operation setting91012V
V(FETON_LP)CHG pin voltage with respect to BAT, DSG pin voltage with respect to LD/PACK, 6 V  ≤ VBAT  ≤ 80 V, VLD  ≤ VDSG(1)(2)VBAT ≥ 6V, CHG/DSG CL = 20nF, RGS = 10MΩ, charge pump low power mode setting678.5
V(FET_UVLO)CHG pin voltage with respect to BAT, DSG pin voltage with respect to LD/PACK, 6 V  ≤ VBAT  ≤  80 V, VLD  ≤ VDSG(1)(2)VBAT ≥ 6V, CHG/DSG CL = 20nF, RGS = 10MΩ, charge pump in normal mode setting4.556.5V
V(FET_UVLO_LP)CHG pin voltage with respect to BAT, DSG pin voltage with respect to LD/PACK, 6 V  ≤ VBAT  ≤ 80 V, VLD  ≤ VDSG(1)(2)VBAT ≥ 6V, CHG/DSG CL = 20nF, RGS = 10MΩ, charge pump UVLO at low power mode setting2.533.5
V(SRCFOL_FETON)DSG on voltage with respect to BATCHG/DSG CL = 20nF, RGS = 10MΩ, source follower mode0V
V(CHGFETOFF)CHG off voltage with respect to BATCHG/DSG CL = 20nF, RGS = 10MΩ, steady state value0.7V
V(DSGFETOFF)DSG off voltage with respect to LD/PACKCHG/DSG CL = 20nF, RGS = 10MΩ, steady state value0.1V
t(CHG/DSG_FET_ON)CHG and DSG rise timeCHG/DSG CL = 20nF,  RGS = 10MΩ, RGATE = 100 Ω, 0.5 V to 4 V gate-source overdrive, charge pump high overdrive setting(4)(5)2140µs
t(CHGFETOFF)CHG fall time to BATCHG CL = 20nF, RGS = 10MΩ, RGATE = 100 Ω, 90% to 10% of V(FETON)(5)4665µs
t(DSGFETOFF)DSG fall time to LD/PACKDSG CL = 20nF, RGATE = 100Ω, RGS = 10MΩ, 90% to 10% of V(FETON)(5)220µs
t(PCHG/PDSG_FET_ON)PCHG and PDSG rise timePCHG/PDSG CL = 5nF, RGS = 10MΩ,  RGATE = 100Ω, 0.5V to 4V gate-source overdrive, charge pump high overdrive setting(4)(5)2140µs
t(PCHGFETOFF)PCHG fall time to BATPCHG CL = 5nF, RGS = 10MΩ, RGATE = 100Ω, 90% to 10% of V(FETON)(5)150250µs
t(PDSGFETOFF)PDSG fall time to LD/PACKPDSG CL = 5nF, RGS = 10MΩ, RGATE = 100Ω, 90% to 10% of V(FETON)(5)150250µs
t(CP_START)Charge pump start up timeCL = 20nF, C(CP1) = 470nF, 10% to 90% of V(FETON)20ms
C(CP1)Charge pump capacitor(3)1004702200nF
(1) Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage.
(2) When the DSG driver is enabled, the CHG driver is disabled, and a voltage is applied at the LD pin such that VLD > VDSG, the voltage at DSG will rise to ≈ VLD - 0.7 V
(3) Specified by design
(4) Specified by characterization
(5) RGATE can be optimized during design and system evaluation for best performance. A larger value may be desired to avoid an overly fast FET turn on/off, which can result in a large voltage transient due to cell and harness inductance.